Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Abstract: The present invention provides a polybenzoxazole precursor, which comprises a structure of formula (I): wherein the definitions of Y, Z, R1, i, j, and V are provided herein. By means of the polybenzoxazole precursor, the resin composition of the present invention is able to form a film with high frequency characteristics and high contrast.

Abstract: The present invention provides a white light LED package structure and a white light source system, which includes a substrate, an LED chip, and a wavelength conversion material layer. The peak emission wavelength of the LED chip is between 400 nm and 425 nm; the peak emission wavelength of the wavelength conversion material layer is between 440 nm and 700 nm, and the wavelength conversion material layer absorbs light emitted from the LED chip and emits a white light source; and the emission spectrum of the white light source is set as P(?), the emission spectrum of a blackbody radiation having the same color temperature as the white light source is S(?), P(?max) is the maximum light intensity within 380-780 nm, S(?max) is the maximum light intensity of the blackbody radiation within 380-780 nm, D(?) is a difference between the spectrum of the white light LED and the spectrum of the blackbody radiation, and within 510-610 nm, the white light source satisfies: D(?)=P(?)/P(?max)?S(?)/S(?max), ?0.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.

Abstract: Hybrid positioning methods and electronic apparatuses are provided. A representative method includes: obtaining initial location information; computing initial moving information based upon the sensor readings; computing estimated location information based on the initial moving information and the initial location information; acquiring geographical location readings if a location update condition is satisfied; generating reference location information based on the geographical location readings acquired; comparing the estimated location information with the reference location information to obtain a deviation information; computing a calibrated moving information based on the estimated location information and the deviation information; and computing a calibrated location information based on the deviation information, calibrated moving information and the estimated location information.

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: A method for preparing a three-dimensional carbon nanotube composite structure comprises: providing a substrate; subjecting the substrate to nickel ion modification treatment to form at least one nickel ion nuclear seed on the substrate; providing a hydrogen gas to pass through the substrate and heating the substrate to a reduction temperature for reducing the nickel ion nuclear seed by the hydrogen gas at the reduction temperature; and supplying a carbon source gas and a protective gas to pass through the substrate and heating the substrate to a growth temperature so that the carbon atoms generated by the carbon source gas through the catalytic cracking of the nickel ion nuclear seed are deposited on the bottom of the nickel ion nuclear seed to form a carbon nanotube gradually, wherein the growth temperature is greater than or equal to the reduction temperature. The three-dimensional carbon nanotube composite structure prepared by the method and its application are also disclosed.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A connection module is disposed in a main circuit board and includes a card edge connector, a hard circuit board and two connectors. The card edge connector is fixedly disposed on the main circuit board. The hard circuit board has a board body and a connecting tongue for correspondingly plugging with the card edge connector. The board body is configured with a disconnecting notch, and the board body is separated by the disconnecting notch into two floating plates arranged side by side at an interval and floatable using the disconnecting notch. The connectors are respectively fixed to the floating plates. Thus, without needing an additional guide frame, the connectors are enabled to float in any desired direction, thereby achieving effects of reducing an overall height and satisfying current thinning requirements.

Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.

Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.