Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.

Abstract: Antibodies that include an antigen binding region that binds to CD137 are provided herein. Also provided herein are bispecific antibodies that include a first antigen binding region that binds to CD137 and a second antigen binding region that binds to an immune checkpoint molecule, an immune stimulatory molecule, or a tumor antigen. Pharmaceutical compositions that include the antibodies and methods of treating cancer are provided.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A power connector is provided, used with a circuit board having conductive holes. The power connector includes an insulating housing and a power terminal group. One end of the insulating housing includes two strip-shaped openings arranged side by side, and the other end includes multiple sockets. A portion of the sockets are arranged in a column aligned with one strip-shaped opening, and the rest of the sockets are arranged in a column aligned with the other strip-shaped opening. Both a positive terminal and a negative terminal of the power terminal group have a conductive plate, with multiple insertion pins extending from one end of the conductive plate, and at least one conductive pin extending from the other end. Each conductive plate is inserted into each strip-shaped opening, each insertion pin is inserted into each socket, and each conductive pin is inserted into each conductive hole.

Abstract: Provided are monospecific and bispecific proteins that bind specifically to PD-L1. Exemplary proteins release the inhibition through PD-L1. Exemplary polyvalent proteins comprise at least one PD-L1 binding site. In certain embodiments, the binding sites may be linked through an immunoglobulin constant region. Anti-PD-L1 antibodies are also provided. A pharmaceutical composition includes the antibody or the antigen-binding portion thereof as above mentioned and at least one pharmaceutically acceptable carrier.

Abstract: A memory device includes a substrate, a word line buried in the substrate and extending in a first direction, a word line cap layer over the word line, a landing pad over and in contact with the substrate and the word line cap layer, a cell contact over and in contact with the landing pad, and a bit line over the word line and extending in a second direction perpendicular to the first direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: An antenna system with switchable radiation gain includes a signal feeding element, a first antenna element, a second antenna element, a first diode, a first switch element, a second switch element, a first impedance transformer, and a second impedance transformer. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first diode has an anode coupled to the first connection point, and a cathode coupled to the second connection point. The first switch element and the second switch element are configured to select either the first impedance transformer or the second impedance transformer as a first target transformer, and the selected first target transformer is coupled between the first connection point and the signal feeding element.

Abstract: A multi-directional output device includes a printed circuit board on which first and second magnetic sensors are arranged, and a direction control unit arranged above the printed circuit board. The direction control unit includes: first and second rotating driving bodies; first and second sliding driving bodies respectively movably connected to the first and second rotating driving bodies; first and second magnets respectively fixed on the first and second sliding driving bodies; and a lower cover on which first and second slide grooves are provided, wherein the first and second sliding driving bodies are respectively slidably arranged in the first and second slide grooves, and the first magnetic sensor and the second magnetic sensor are arranged corresponding to the first slide groove and the second slide groove, respectively.

Abstract: The disclosure relates to a method and system for processing information in a content delivery network (CDN). The method includes: obtaining total bandwidth values at respective sampling time points within a management cycle, and arranging the total bandwidth values in chronological order; determining an interval between a first sampling time point and a second sampling time point as a management interval; determining usage ratios of respective bandwidth users according to a first bandwidth value used within the management interval by the bandwidth users sharing the CDN bandwidth, and a second bandwidth value in total used within the management interval by all of the bandwidth users sharing the CDN bandwidth; and managing, based on the usage ratios, bandwidth usage by the respective bandwidth users.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: Embodiments of this specification provide signature authentication methods and apparatuses. A service private key for signature authentication is embedded in a trusted execution environment (TEE) of a terminal device in which a client device is located. In an implementation, a method includes the following. The client device sends a signature authentication request to a server. The client device receives authentication data information sent from the server. The client device encrypts the authentication data information by using a key that is pre-synchronized with the TEE. The client device sends encrypted authentication data information to the TEE. The client device then receives the signature data sent from the TEE and sends the signature data to the server.