Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

Abstract: A method for data radio bearer management, the method including: transmitting a data radio bearer (DRB) setup request message to a wireless communication node; receiving a DRB setup response message from the wireless communication node, determining at least one DRB and at least one Quality of Service (QoS) flow mapped to the at least one DRB supported by the wireless communication node; and configuring the wireless communication node to support the at least one DRB and the at least one QoS flow.

Abstract: A foldable display device is provided by the present disclosure. The foldable display device includes a foldable display panel and a foldable cover. The foldable cover is adhered to the foldable display panel. The foldable cover includes an inner substrate, an outer substrate and a first adhesive. The first adhesive is disposed between the inner substrate and the outer substrate. A thickness of the first adhesive is ranged from 1 micrometer to 40 micrometers, and a ratio of the sum of the thickness of the first adhesive and a thickness of the inner substrate to a thickness of the foldable cover is greater than or equal to 0.5 and less than 1. In addition, the foldable display device further includes a second adhesive disposed between the foldable display panel and the foldable cover.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: An electronic device which is capable of being bent in a first direction and includes a plurality of light-emitting units and a plurality of conductive patterns overlapping with at least a portion of the plurality of light-emitting units and extending in a second direction. The first direction and the second direction have an angle ? of not greater than 30 degrees.

Abstract: A foldable stand has a base, a riser, and a switching mechanism. The riser is located on the base. The switching mechanism connects the base and the riser such that the riser selectively pivots relative to the base from an upright position to a folded position. The switching mechanism has a locked status and a released status. In the locked status, the switching mechanism prevents the riser from pivoting relative to the base. In the released status, the switching mechanism allows the riser to pivot relative to the base from an upright position to a folded position. The switching mechanism is configured to be switched from the locked status to the released status by rotation of the riser around a centerline of the riser.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A DC brushless motor is provided, which includes a housing, a motor assembly, a control board and a dividing plate. Wherein, the motor assembly is arranged in the housing, and a connecting terminal is arranged on it. The control board is arranged in the housing and electrically connected with the connecting terminal. The dividing plate is arranged in the housing and is used to divide the motor assembly from the control board. The disclosure is used to solve a problem of complicated internal wiring of a motor caused by a division of the motor and a controller of the conventional DC brushless motor.

Abstract: A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

Abstract: The present disclosure discloses an optical imaging lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The first lens has negative refractive power; the second lens has negative refractive power; the third lens has positive refractive power; the fourth lens has positive refractive power; the fifth lens has refractive power, and an object-side surface thereof is a concave surface; the sixth lens has refractive power; and the seventh lens has negative refractive power. An effective focal length f1 of the first lens and a total effective focal length f of the optical imaging lens assembly satisfy ?3.5<f1/f<0.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.

Abstract: The present invention discloses a straight-line sewage treatment system for enhanced treatment of low-carbon-to-nitrogen ratio (C/N) domestic sewage, including a sewage intake tank, an enhanced denitrification tank through a pipeline, an effluent outlet of the enhanced denitrification tank, an effluent pipe, a first storage tank, a second storage tank, and a disinfection tank.

Abstract: The disclosure provides a control method of a display driver. The control method includes receiving address information and defining an IC address according to the address information. The IC address includes n bits representing k zones, and n and k are positive integers. The control method further includes receiving the IC address, a black frame data signal and a pulse-width modulation (PWM) signal, and turning on or off the plurality of LEDs in the corresponding zone according to toggle of bit in the black frame data signal. Each bit in the black frame data signal indicates that a plurality of LEDs in a zone among the k zones are turned on or off.

Abstract: A machine learning method includes: distinguishing foregrounds and backgrounds of a first image to generate a first mask image; cropping the first image to generate second and third images; cropping the first mask image to generate second and third mask images, wherein a position of the second mask image and a position of the third mask image correspond to a position of the second image and a position of the third image, respectively; generating a first feature vector group of the second image and a second feature vector group of the third image by a model; generating a first matrix according to the first and second feature vector groups; generating a second matrix according to the second and third mask images; generating a function according to the first and second matrices; and adjusting the model according to the function.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A computer-implemented method for communication channel management performed by a wireless access point (AP) device is described. An original management frame that carries a target information element is constructed, where the target information element includes an information element related to communication channel management. When determined that one or more clients are connected to the AP device, for each of the determined clients: A destination address of the original management frame is set to a MAC address of the client. To obtain an encrypted management frame by using a key corresponding to the client, information in the target information element is encrypted. The encrypted management frame is sent in a WiFi network, so that a connected client in the WiFi network determines, based on the destination address, whether to process the encrypted management frame.