Abstract: This specification provides methods, computer-readable media, and apparatuses for signature authentication. A server performs signature authentication on a terminal device. A service private key required for signature authentication is embedded in a trusted execution environment (TEE) of the terminal device. The TEE verifies a biological feature entered by a user, and after verification succeeds, the TEE completes a signature required by a signature authentication request.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

Abstract: A fastener structure and an assembly method thereof are introduced. The fastener structure includes a body and a fastener. The body has a limiting structure and is for assembling at a first object. The fastener and the body are movably assembled. The fastener has a limiting portion, which coordinates with the limiting structure to limit a movement stroke of the fastener, so as to engage or disengage the fastener with or from a second object. Thus, the body can be assembled with the first object and the fastener can be engaged with or disengaged from the second object so as to complete quick coupling and separation of two objects, further achieving effects of repeated quick coupling and separation.

Abstract: A method for re-triggering wakeup to handle time skew between a scalar operation and a vector operation is provided. The method includes: initiating, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop; triggering a speculative wakeup from the LD pipeline during an execution of the respective load operation; triggering a second wakeup corresponding to the speculative wakeup from the LD pipeline; and waking up, based on the second wakeup, the vector micro-operation in the baler issue queue of the baler unit.

Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.

Abstract: A method of forming a semiconductor device is provided. The method includes mounting a semiconductor die on a die pad of a leadframe. The die pad includes a central opening configured to expose a central portion of the semiconductor die. A first end of a bond wire is attached to a bond pad of the semiconductor die and a second end of the bond wire is attached to a lead of the leadframe. An encapsulant encapsulates the semiconductor die and the leadframe. A portion of the lead and a portion of the die pad are exposed and protruded through the encapsulant.

Abstract: A heat pipe comprises a flat tube and a wick structure. The flat tube includes a hollow chamber and has a front and a rear sealed ends along an axial direction. The wick structure is disposed in the hollow chamber and extended along the axial direction of the flat tube. The wick structure is divided into a front, a middle and a rear sections sequentially along the axial direction. The front section is near the front sealed end, the rear section is near the rear sealed end. The front, middle and rear sections have a maximum length parallel to the width direction, respectively. The maximum length of the front section is greater than that of the middle section, and the maximum length of the middle section is greater than that of the rear section.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A curable composition includes an epoxy monomer component and an aniline-based hardener. The epoxy monomer component is a first component formed from a first epoxy monomer represented by Formula (I), or a second component including the first epoxy monomer represented by Formula (I) and a second epoxy monomer different from the first epoxy monomer represented by Formula (I), wherein each of the substituents in Formula (I) is given the definitions as set forth in the Specification and Claims. Based on 100 wt % of the epoxy monomer component, an amount of the first epoxy monomer represented by Formula (I) is not smaller than 25 wt % and less than 100 wt % and an amount of the second epoxy monomer is greater than 0% and not greater than 75 wt %. A cured product formed from the curable composition, and a method for encapsulating a semiconductor device using the curable composition are also provided.

Abstract: A gate driver circuit including seven transistors and two capacitors is provided. A first end of a third transistor is coupled to a first pulse signal, a second end of the third transistor outputs a gate signal, and a control end of the third transistor is coupled to a first end of a second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a second end of the fourth transistor is coupled to a first voltage, and a control end of the fourth transistor is coupled to a control end of the second transistor. A first end of a fifth transistor is coupled to a second voltage, a second end of the fifth transistor is coupled to the control end of the fourth transistor, and a control end of the fifth transistor is coupled to a second pulse signal.

Abstract: An encoder with a light emitting diode includes: a light emitting diode, a switch module, an encoder module and a control shaft. The switch module includes an insulating base having a terminal part, a conductive elastic piece and a pressing driving body. The conductive elastic piece is disposed in the insulating base, and is disposed above the terminal part. The pressing driving body is disposed in the insulating base and is disposed above the conductive elastic piece for accommodating the light emitting diode. At least part of the encoder module is disposed in the insulating base, and the encoder module includes a magnetic sensor, a magnetic ring and a rotating driving body. The control shaft passes through a penetration hole of the rotating driving body, and is disposed above the pressing driving body.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes an interconnect structure, a passivation layer and a conductive bump structure. The interconnect structure includes a conductive pad located at a top of the interconnect structure. The passivation layer is disposed on the interconnect structure. The conductive bump structure is disposed on and embedded into the passivation layer and the conductive pad. In a first direction, a first interface between the passivation layer and the conductive pad is located beside and misaligned with a second interface between the conductive bump structure and the conductive pad.

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A coring device, comprising an electronic sub communicated with a ground control system and identifying the position of a core taken underground, a supporting arm sub for fixing the coring device, a rotating sub for rotating a mechanical sub to a specified position to carry out coring by rotating, a hydraulically controlled sub for providing power to the rotating sub and the mechanical sub, a mechanical sub for performing pushing, coring, core folding and core length measurement operations, and a core storage barrel sub for storing a taken core, which are sequentially connected. The rotating sub comprises a rotating shaft, a moving sleeve which sleeves the rotating shaft and is in threaded connection with the rotating shaft, and a fixed housing; the rotating shaft and the moving sleeve are arranged inside the fixed housing, two ends of the rotating shaft respectively extend from two ends of the fixed housing.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.