Abstract: A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.

Abstract: A docking station includes a casing, a socket and a plurality of peripheral interface devices. The casing includes a base and a cover, wherein the cover is pivotingly disposed on the base, openably and coverably, to form an appearance of a notebook computer. The socket is formed in a surface of the base for receiving a mobile communication device, and a high speed transmission interface is formed in a bottom of the socket. The plurality of peripheral interface devices is disposed on the casing and electrically connected with the high speed transmission interface. When the mobile communication device is placed in the socket, the mobile communication device is electrically connected with the high speed transmission interface and transmits signals with the plurality of peripheral interface devices. Basing on the structure, the present invention can ensure that mobile communication devices are convenient for operation.

Abstract: Disclosed is a distributed controlled passive optical network system and bandwidth control method thereof. The system comprises an optical line terminal (OLT), plural optical network units (ONUs) and a splitter with combiner. Each ONU has a first Tx/Rx for respectively transmitting and receiving data packets on an upstream data channel and a downstream data channel, and a second Tx/Rx for transmitting and receiving control signals/commands on a control channel. Upstream data of each ONU is carried by the upstream data channel and sent to the OLT through the splitter with combiner. Downstream data of the OLT is carried by the downstream data channel and sent to corresponding ONUs through the splitter with combiner. With the control signals/commands carried by the control channel, the required information of network status among the ONUs is provided.

Abstract: An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced.

Abstract: Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Abstract: A sliding flat panel display and keyboard module for monitoring and controlling server computers on a server rack is described. The sliding flat panel display and keyboard module has an L-shaped supporting frame, a vertical sliding rail, a horizontal sliding rail, a flat panel display, and a keyboard. The vertical sliding rail and the horizontal sliding rail are respectively disposed on a vertical surface and a horizontal surface of the L-shaped supporting frame. The flat panel display couples to the vertical sliding rail and the keyboard couples to the horizontal sliding rail, so that the flat panel display and the keyboard are able to slide on the L-shaped supporting frame horizontally.

Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

Abstract: A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate.

Abstract: Disclosed is a distributed controlled passive optical network system and bandwidth control method thereof. The system comprises an optical line terminal (OLT), plural optical network units (ONUs) and a splitter with combiner. Each ONU has a first Tx/Rx for respectively transmitting and receiving data packets on an upstream data channel and a downstream data channel, and a second Tx/Rx for transmitting and receiving control signals/commands on a control channel. Upstream data of each ONU is carried by the upstream data channel and sent to the OLT through the splitter with combiner. Downstream data of the OLT is carried by the downstream data channel and sent to corresponding ONUs through the splitter with combiner.

Abstract: A rack-mounted KVM module is configured for a server rack. An L-shaped supporting frame, which has a vertical plane and a horizontal plane, is coupled to the sever rack. A flat panel display is coupled to the vertical sliding rail to move along the L-shaped supporting frame horizontally. A keyboard module is coupled to the horizontal sliding rail to move along the L-shaped supporting frame horizontally. A positioning mechanism is disposed in the horizontal sliding rail. The positioning mechanism consists mainly of an outer rail, an inner rail, a link bracket, a latch and a positioning switch. The latch is swiveled to engage a notch of the latch in a block portion of the outer rail or to remove the notch thereof from the block portion to respectively lock or unlock a fixed position when the link bracket is slid along the inner rail by moving the positioning switch.

Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.

Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.

Abstract: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.

Abstract: An aqueous solution for polishing and deburring includes pure water; carboxylic acid of 200 gram per liter to 300 gram per liter; sulfuric acid ions of 200 gram per liter to 500 gram per liter; phosphoric acid ions of 100 gram per liter to 300 gram per liter; and nitric acid ions of 50 gram per liter to 200 gram per liter. Also, a process for polishing and deburring a part made of pure nickel or nickel-200 in the solution includes removing oily substance from the part; washing the part by water; pouring the solution into a bath and submerging the part in the solution so that the part is brought into contact with the solution; neutralizing the solution remained on the surface of the part to prevent the part from oxidizing; and drying the part to obtain a finished part.

Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.

Abstract: A method for exposure is provided to avoid a rise in temperature of a lens set. First, a light beam passes through a first light-receiving region of the lens set to expose a pattern on a substrate, and the first light-receiving region has a rise in temperature. Thereafter, the first light-receiving region is moved away. Afterwards, the light beam passes through a second light-receiving region of the lens set so that the first light-receiving region has a drop in temperature.

Abstract: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.