Abstract: A method and apparatus for performing text-to-speech conversion in a client/server environment partitions an otherwise conventional text-to-speech conversion algorithm into two portions: a first “text analysis” portion, which generates from an original input text an intermediate representation thereof; and a second “speech synthesis” portion, which synthesizes speech waveforms from the intermediate representation generated by the first portion (i.e., the text analysis portion). The text analysis portion of the algorithm is executed exclusively on a server while the speech synthesis portion is executed exclusively on a client which may be associated therewith. The client may comprise a hand-held device such as, for example, a cell phone, and the intermediate representation of the input text advantageously comprises at least a sequence of phonemes representative of the input text.

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: Multiple, yet plausible, pronunciations of a proper name are generated based on one or more potential language origins of the name, and based further on the context in which the name is being spoken—namely, on characteristics of the population of potential speakers. Conventional techniques may be employed to identify likely candidates for the language origin of the name, and the characteristics of the speaker population on which the generation of the pronunciations is further based may comprise, for example, the national origin of the speakers, the purpose of the speech, the geographical location of the speakers, or the general level of sophistication of the speaker population.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A sense amplifier circuit for a memory integrated circuit provides good performance and relatively low power consumption. The circuitry includes a cascode output and a feedback (214) from the cascode output to a transistor (M1) to provide additional pull-up current at a bit line (206).

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

Abstract: A Color fax/video printing means for a digital still camera (DSC) which integrate the structure and function of fax, video signal, copying, printing and data communication apparatus in a whole and adopts method and structure such as computer architecture, central processing unit, data communication, DSC, ink-jet printing or laser printing, embedded circuit, firmware, dual bus, ASIC, programmable, cell active and pin sharing etc. to achieve advantages of enhancing efficiency, simplifying structure and operation, reducing cost and power consumption.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.