Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.

Abstract: The present invention provides a data analytic scheme for screening biomarkers for differential diagnosis of the status of Parkinson's disease, Parkinson's disease with mild cognitive impairment, Parkinson's disease dementia, Alzheimer's disease, and/or multiple system atrophy, the methodology implementing the same and the results of the screening thereof. Biomedical Oriented Logistic Dantzig Selector (BOLD Selector) was developed to identify candidate microRNAs and extracellular vesicle proteins effective at discerning between any two of the above mentioned disease categories from profiling results. The prediction models are finalized by establishing logistic regression formula for each pair of patient group differentiation.

Abstract: The invention discloses a blockchain-based intrusion detection system for railway signal, which is built on a blockchain's distributed chain structure, without a central, trusted control center. This design mitigates the vulnerabilities associated with centralized intrusion detection centers. Additionally, by utilizing a blockchain-based distributed structure, it also eliminates the risk of a single point of failure for the intrusion detection center. Moreover, the data within the blockchain-based intrusion detection system is highly resistant to malicious tampering. This is achieved by leveraging the consensus mechanism inherent in the blockchain, which can achieve consensus among intrusion detection nodes. The current invention solves the internal evil attacks and avoid the inability to reach consensus between nodes due to internal evil, thereby affecting the intrusion detection performance; at the same time, the intrusion detection model can resist external network attacks.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: A semiconductor structure including a substrate and a capacitor structure is provided. The capacitor structure is disposed above the substrate. The capacitor structure includes a first electrode layer, a second electrode layer, and a first dielectric layer. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first dielectric layer is a composite dielectric layer including at least one first silicon nitride layer and at least one first high-k dielectric layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A transparent projection screen and a manufacturing method. The transparent projection screen is for receiving projection light and transmitting ambient light and comprises a first substrate layer, a Fresnel structure layer, a surface diffusion layer, a nano metal plating layer, and a binding adhesive layer. The Fresnel structure layer is disposed on the first substrate layer and comprises a prism surface. The surface diffusion layer is disposed on a portion of the prism surface. The nano metal plating layer is disposed on the surface diffusion layer. The binding adhesive layer is disposed on the nano metal plating layer and fills and levels the prism surface. The projection light passes the first substrate layer and is incident on the prism surface and then reflected thereby. The ambient light passes the binding adhesive layer, the nano metal plating layer, the surface diffusion layer and the first substrate layer, and is emitted.

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

Abstract: Provided are a salt form of an estrogen receptor down-regulator, a crystalline form thereof, and a preparation method therefor

Abstract: A semiconductor memory device includes a substrate, a first interlayer dielectric layer, a second interlayer dielectric layer, a via in the second interlayer dielectric layer in a memory region, and a data storage structure on the via. The second interlayer dielectric layer includes a first recess structure and a second recess structure. The first recess structure has a first recessed thickness between the bottom surface of the data storage structure and the lowest point of the second interlayer dielectric layer in the memory area. The second recess structure has a second recessed thickness between the bottom surface of the data storage structure and the lowest point of the logic circuit region. The first recessed thickness ranges between 300-650 angstroms, and the second recessed thickness ranges between 300-800 angstroms.

Abstract: Examples of the present disclosure provide a method and an apparatus for denoising a low-light image, wherein the method includes: acquiring a low-light image in RAW domain; performing a preset image enhancement transformation on the low-light image in the RAW domain, and inputting the transformed image into a pre-trained denoising network model to obtain an output image; wherein, the denoising network model is trained based on sample images, and the sample images include a low-light image with simulated dead pixels and a noiseless image; performing an inverse transformation of the preset image enhancement transformation on the output image to obtain a denoised image. It can significantly reduce the influence of dead pixels of images on the process of denoising the low-light image and improve the quality of low-light image denoising.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on a substrate, forming a first trench in the IMD layer, forming a metal layer in the first trench, planarizing the metal layer to form a first metal interconnection in the IMD layer and a first recess atop the first metal interconnection, and then forming a first bottom electrode (BE) in the first recess.

Abstract: A semiconductor memory device includes a substrate, a first interlayer dielectric layer on the substrate, a second interlayer dielectric layer on the first interlayer dielectric layer, a via positioned in the second interlayer dielectric layer in the memory region, and a data storage structure stacked on the via. The second interlayer dielectric layer has a first minimum thickness in the memory region and a second minimum thickness in the logic circuit region, wherein the difference between the first minimum thickness and the second minimum thickness is less than or equal to 150 angstroms.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer on the MTJ, forming a first inter-metal dielectric (IMD) layer on the first cap layer, forming a second cap layer on the first cap layer and the first IMD layer, forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer, and then planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A magnetic random access memory structure includes a first dielectric layer; a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; and a spacer layer surrounding the protective layer.

Abstract: A backplane connector includes a shielded design that has wafers with signal terminals supported as edge-coupled terminal pairs for differential signaling. A ground shield is mounted on each wafer and provides a U-channel that partially shields each terminal pair. An insert can be provided to help connect the ground shield to a U-shield to provide U-shaped shielding structure substantially the entire way from a tail to a contact.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: A magnetic random access memory structure includes a first dielectric layer, a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; a mask layer surrounding the protective layer, and a spacer layer surrounding the mask layer and the protective layer.

Abstract: The embodiments of the present application provide a denoising method, apparatus, electronic device and medium, which relates to the technical field of image processing. The method comprises: inputting an image to be processed into an image denoising model, which is a model obtained by training a convolutional neural network model based on a preset training set, wherein the preset training set includes multiple groups of annotation data and sample data corresponding to each group of annotation data, and each group of annotation data includes multiple noiseless images obtained by performing motion simulation processing on one reference noiseless image, and the sample data corresponding to the group of annotation data includes images obtained by superimposing noise to the multiple noiseless images respectively; acquiring denoised image data output by the image denoising model; converting the image data into an image, to obtain a denoised image corresponding to the image to be processed.