Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 ?m. Corresponding methods of producing multi-chip assemblies are also described.

Abstract: A use of a hemimellitic acid ester of formula I as a base oil a lubricant composition for lubricating tribological systems. In some embodiments, R1, R2 and R3, are independently of one another: a C5 to C20 aromatic group, a C5 to C20 cycloalkyl group, an unsubstituted, branched or unbranched C1 to C20 alkyl group, and/or a C1 to C5 alkyl group comprising at least one substituent selected from the group consisting of cycloalkyl groups and aromatic groups. In some embodiments, the hemimellitic acid ester of formula I is provided as a mixture of different compounds of formula I and/or the hemimellitic acid ester of formula I comprises groups R1, R2 and R3 at least partially differing from one another.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: An air-material mixing and spraying actuator, which relates to the field of devices for spraying materials to deep soil. The actuator includes a material mixing and spraying pipe, a material temporary storage assembly, a second material supply assembly and a compressed air supply assembly, where a material discharge outlet is provided at one end of the material mixing and spraying pipe; the material temporary storage assembly is disposed at one end of the material mixing and spraying pipe to temporarily store materials; the second material supply assembly communicates with the material temporary storage assembly and sends materials to the material temporary storage assembly; and the compressed air supply assembly communicates with the material temporary storage assembly and provides high-pressure air that bursts the soil to form cracks or achieve an uplift effect, and spray the materials temporarily stored to the cracks in cooperation with the material temporary storage assembly.

Abstract: One or more embodiments of this specification provide a processing method, including: when a first coroutine is executed, determining whether a to-be-fetched object in an execution process is stored in a target cache; and if it is determined that the to-be-fetched object is not stored in the target cache, prefetching the to-be-fetched object, and switching the currently executed first coroutine to a second coroutine. According to the processing method provided in the embodiments of this specification, a throughput capability of a CPU can be improved.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric. A method of producing the semiconductor device is also described.

Abstract: The present application relates to the technical field of genetic breeding, and provides a method for identifying whether a diploid potato is self-compatible. The method relates to identifying whether a StSCI gene in the diploid potato is transcribed and expressed. Also disclosed is a method for identifying whether a StSCI gene is expressed by using molecular marker, and a method of screening for the molecular marker, which includes: obtaining the genome sequence information of parental materials, screening for difference sites of the parental materials, screening for the molecular marker, and identifying whether the screened molecular marker are usable. As for the identification of the self-compatibility of a diploid potato by using the screened molecular marker, the identification workload is small, a lot of time is saved, and the identification result is not affected by the environment, and it is accurate and reliable.

Abstract: An approach is disclosed that receives an incoming data record, the data record including a number of data fields. The approach determines a current Real-Time Resources Score (RTRS). The RTRS being a forecast of the information handling system's ability to handle incoming data transmissions. When the RTRS is lower than a current data accumulation rate, a subset of the data record is sent based on field priorities. The approach assigns priorities to each of the data fields included in the data record based on a priority assessment of the respective data fields. The approach then sends, to a data receiver, a subset of the plurality of data fields based on the assigned priority.

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.

Abstract: The invention relates to ester compounds of the general formula (I) to a process for preparation thereof and to the use thereof. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 ?m. Corresponding methods of producing multi-chip assemblies are also described.

Abstract: The present invention provides novel compositions and methods for assessing the size of tandem repeat sequences, e.g., telomeres, within a genome, using specially designed Molecular Inversion Probes (MIPs) and reaction conditions.

Abstract: A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

Abstract: Methods and electronic circuits for executing instructions in a central processing unit (CPU) are provided. One of the methods includes forming an instruction block by sequentially fetching, from a current thread queue, one or more instructions including one jump instruction, wherein the jump instruction is the last instruction in the instruction block; transmitting the instruction block to a CPU execution unit for execution; replenishing the current thread queue with at least one instruction to form a thread queue to be executed; determining a target instruction of the jump instruction according to an execution result of the CPU execution unit; determining whether the target instruction is contained in the thread queue to be executed; and if not, flushing the thread queue to be executed, obtaining the target instruction and adding the target instruction to the thread queue to be executed.

Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.