Abstract: The present invention relates to the technical field of endoscopes, and discloses a confocal endoscope with a fixing device.

Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.

Abstract: The invention relates to ester compounds of the general formula (I) to a process for preparation thereof and to the use thereof. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 ?m. Corresponding methods of producing multi-chip assemblies are also described.

Abstract: The present invention provides novel compositions and methods for assessing the size of tandem repeat sequences, e.g., telomeres, within a genome, using specially designed Molecular Inversion Probes (MIPs) and reaction conditions.

Abstract: A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

Abstract: Methods and electronic circuits for executing instructions in a central processing unit (CPU) are provided. One of the methods includes forming an instruction block by sequentially fetching, from a current thread queue, one or more instructions including one jump instruction, wherein the jump instruction is the last instruction in the instruction block; transmitting the instruction block to a CPU execution unit for execution; replenishing the current thread queue with at least one instruction to form a thread queue to be executed; determining a target instruction of the jump instruction according to an execution result of the CPU execution unit; determining whether the target instruction is contained in the thread queue to be executed; and if not, flushing the thread queue to be executed, obtaining the target instruction and adding the target instruction to the thread queue to be executed.

Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.

Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

Abstract: The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.

Abstract: Provided is a StSCI protein for changing the self-incompatibility of diploid potato materials, wherein the amino acid sequence of the StSCI protein includes or consists of the following sequence: 1) the amino acid sequence represented by SEQ ID NO: 1; or 2) a functional homologous sequence having at least 95% sequence identity with the amino acid sequence represented by SEQ ID NO: 1; or 3) a protein in which one or more (e.g., 1-10) amino acids are added, deleted, or replaced in the amino acid sequence represented by SEQ ID NO: 1 and has the activity of inhibiting self-incompatibility. The advantage of the application is that the StSCI protein may inhibit the cytotoxicity of multiple types of S-RNase, which is hereditary and fundamentally overcomes the defect of self-incompatibility of diploid potatoes, thereby facilitating to realize the cultivation of a high-generation homozygous inbred line of diploid potatoes.

Abstract: The present application relates to the technical field of genetic breeding, and provides a method for identifying whether a diploid potato is self-compatible. The method relates to identifying whether a StSCI gene in the diploid potato is transcribed and expressed. Also disclosed is a method for identifying whether a StSCI gene is expressed by using molecular marker, and a method of screening for the molecular marker, which includes: obtaining the genome sequence information of parental materials, screening for difference sites of the parental materials, screening for the molecular marker, and identifying whether the screened molecular marker are usable. As for the identification of the self-compatibility of a diploid potato by using the screened molecular marker, the identification workload is small, a lot of time is saved, and the identification result is not affected by the environment, and it is accurate and reliable.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.