Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

Abstract: The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.

Abstract: The present application relates to the technical field of genetic breeding, and provides a method for identifying whether a diploid potato is self-compatible. The method relates to identifying whether a StSCI gene in the diploid potato is transcribed and expressed. Also disclosed is a method for identifying whether a StSCI gene is expressed by using molecular marker, and a method of screening for the molecular marker, which includes: obtaining the genome sequence information of parental materials, screening for difference sites of the parental materials, screening for the molecular marker, and identifying whether the screened molecular marker are usable. As for the identification of the self-compatibility of a diploid potato by using the screened molecular marker, the identification workload is small, a lot of time is saved, and the identification result is not affected by the environment, and it is accurate and reliable.

Abstract: Provided is a StSCI protein for changing the self-incompatibility of diploid potato materials, wherein the amino acid sequence of the StSCI protein includes or consists of the following sequence: 1) the amino acid sequence represented by SEQ ID NO: 1; or 2) a functional homologous sequence having at least 95% sequence identity with the amino acid sequence represented by SEQ ID NO: 1; or 3) a protein in which one or more (e.g., 1-10) amino acids are added, deleted, or replaced in the amino acid sequence represented by SEQ ID NO: 1 and has the activity of inhibiting self-incompatibility. The advantage of the application is that the StSCI protein may inhibit the cytotoxicity of multiple types of S-RNase, which is hereditary and fundamentally overcomes the defect of self-incompatibility of diploid potatoes, thereby facilitating to realize the cultivation of a high-generation homozygous inbred line of diploid potatoes.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.

Abstract: Described herein are a process for the preparation of poly(ester urea) microcapsules, and such poly(ester urea) microcapsules. Perfuming compositions and consumer products including such microcapsules, in particular perfumed consumer products in the form of home care or personal care products, are also described.

Abstract: Described herein are a process for the preparation of a microcapsule slurry, and the microcapsule slurry. Perfuming compositions and consumer products including the microcapsule slurry, in particular perfumed consumer products in the form of home care or personal care products, are also described.

Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

Abstract: A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.

Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: A computer-implemented method for multi-thread processing, the method including: compiling a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; and fusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread including thread portions corresponding to each thread of the first plurality of threads, in which the first instructions include load effective address instructions and control transfer instructions, in which the load effective address instructions and the control transfer instructions are compiled using a second register set, and in which jump operations between thread portions are implemented by the control transfer instructions inserted into the machine instruction code of the fused thread

Abstract: Ester compounds, such as for use in a lubricant, are based on di-, tri- or higher functional carboxylic acids according to formula (I).

Abstract: Embodiments of the specification provide a method and an apparatus for updating shared data in a multi-core processor environment. The multi-processor environment comprises a multi-core processor. The multi-core processor comprises a plurality of separate processing units (referred to as cores, or core processing units (CPUs) in the specification); the multi-core processor is configured to process a multi-threaded task; the multi-threaded task has shared data to update. The method is executed by any CPU. The method may comprise: requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; and setting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index.

Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.

Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

Abstract: Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.