Patents by Inventor Ling Tan

Ling Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404995
    Abstract: An apparatus includes selectable a circuit placement mechanism configured to support two or more different circuit layouts. The circuit placement mechanism may include an overlap of electrical connections associated with the two or more circuit layouts and joined through an etch back selector. The etch back selector may enable the apparatus to function according to a selected one of the two or more different circuit layouts.
    Type: Application
    Filed: April 25, 2024
    Publication date: December 5, 2024
    Inventors: Chin Hui Chong, Hong Wan Ng, See Hiong Leow, Ling Pan, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 12140974
    Abstract: The present disclosure relates to a method for stochastic inspections on power grid lines based on unmanned aerial vehicle-assisted edge computing. According to the method, a stochastic distributed inspection unmanned aerial vehicle is adopted to acquire video images on a target power grid area, which can reduce funds and time costs of inspections. With assistance of superior unmanned aerial vehicle, a goal is to minimize energy consumption of an unmanned aerial vehicle system and extend operation time of the unmanned aerial vehicles under same payload conditions, while processing video image data collected from the inspection unmanned aerial vehicles. The near-far effect generated by communications between mobile unmanned aerial vehicles is eliminated by introducing a NOMA, and position coordinates, system resource allocations and task offload decision schemes are solved by using a method of combining a DDPG algorithm in a Deep reinforcement learning with a genetic algorithm.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: November 12, 2024
    Assignee: NANJING UNIVERSITY OF INFORMATION SCIENCE & TECHNOLOGY
    Inventors: Ling Tan, Lei Sun, Jingming Xia
  • Publication number: 20240353861
    Abstract: The present disclosure relates to a method for stochastic inspections on power grid lines based on unmanned aerial vehicle-assisted edge computing. According to the method, a stochastic distributed inspection unmanned aerial vehicle is adopted to acquire video images on a target power grid area, which can reduce funds and time costs of inspections. With assistance of superior unmanned aerial vehicle, a goal is to minimize energy consumption of an unmanned aerial vehicle system and extend operation time of the unmanned aerial vehicles under same payload conditions, while processing video image data collected from the inspection unmanned aerial vehicles. The near-far effect generated by communications between mobile unmanned aerial vehicles is eliminated by introducing a NOMA, and position coordinates, system resource allocations and task offload decision schemes are solved by using a method of combining a DDPG algorithm in a Deep reinforcement learning with a genetic algorithm.
    Type: Application
    Filed: November 8, 2022
    Publication date: October 24, 2024
    Applicant: NANJING UNIVERSITY OF INFORMATION SCIENCE & TECHNOLOGY
    Inventors: Ling TAN, Lei SUN, Jingming XIA
  • Patent number: 12112997
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
  • Publication number: 20240312890
    Abstract: At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.
    Type: Application
    Filed: February 15, 2024
    Publication date: September 19, 2024
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20240305419
    Abstract: The present disclosure is related to a method and communication device for transport block size determination for a multi-slot transport block transmission and a method and communication device for code block segmentation for a multi-slot transport block transmission. The method for determining a size of a multi-slot transport block (TB) for a multi-slot TB-based transmission includes: determining a number of resource elements (REs) for the transmission; determining a number of information bits at least partially based on one or more of the determined number of REs, a modulation order for the transmission, a target coding rate for the transmission, and a number of layers for the transmission; and determining the size of the multi-slot TB for the transmission at least partially based on the determined number of information bits.
    Type: Application
    Filed: January 14, 2022
    Publication date: September 12, 2024
    Inventors: Ling SU, Zhipeng LIN, Yuande TAN, Robert Mark HARRISON
  • Publication number: 20240304598
    Abstract: A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.
    Type: Application
    Filed: January 26, 2024
    Publication date: September 12, 2024
    Inventors: Chin Hui Chong, Seng Kim Dalson Ye, Hong Wan Ng, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Patent number: 12080628
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
  • Publication number: 20240281499
    Abstract: This application relates to similarity calculation apparatuses and methods, and storage devices. An example similarity calculation apparatus includes an input signal processing circuit, a data calculator, and at least one output processing circuit, where the data calculator includes a storage array configured to store to-be-calculated data. The input signal processing circuit is configured to: generate an operating voltage based on similarity calculation instructions, and convert an address of the to-be-calculated data in the similarity calculation instructions into a target address The data calculator is configured to: select, based on the target address, the to-be-calculated data stored in the storage array, and apply the operating voltage to the to-be-calculated data to perform similarity calculation. The at least one output processing circuit is configured to: process a signal output by the data calculator, and output a calculation result.
    Type: Application
    Filed: April 30, 2024
    Publication date: August 22, 2024
    Inventors: Long CHENG, Ling YANG, Yi LI, Haibo TAN, Guiyou PU
  • Patent number: 12054362
    Abstract: A crane counterweight block alignment detection and control method, a crane counterweight block alignment detection and control device, and a crane. The crane counterweight block alignment detection and control method comprise: a counterweight block being provided with mounting holes for matching with positioning pins on a crane, detecting the center position of the counterweight block, and calculating the relative offset between the center position and the position of the positioning pins; detecting the relative positions of the mounting holes in the counterweight block and the positioning pins, and calculating, according to the positions, a relative rotation angle of the counterweight block for aligning the mounting holes with the positioning pins; and controlling, according to the relative offset and relative rotation angle, the movement of the counterweight block to enable the mounting holes in the counterweight block to be aligned with and installed onto the positioning pins.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: August 6, 2024
    Assignee: ZOOMLION HEAVY INDUSTRY SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Zhiren Tan, Qing Fan, Ling Fu, Yanbin Liu, Yang Zeng, Baike Xu, Hong Wu, Jimei Guo, Zan Huang
  • Patent number: 11966807
    Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: April 23, 2024
    Assignee: Nanjing University of Information Science and Technology
    Inventors: Jian Su, Jialin Zhou, Wei Zhuang, Ling Tan
  • Publication number: 20240074984
    Abstract: The present invention relates to a method of forming polymeric microparticles housing live microorganisms, the method using the steps of (a) providing a microbial solution comprising a crosslinkable polymeric material compatible with live microorganisms; a protective agent; a microbial population; and water; and a crosslinking agent solution comprising a crosslinking agent and water; and (b) subjecting the microbial and crosslinking agent solutions to spray-drying using a co-axial nozzle configured to spray at least three fluids independently, thereby producing microparticles of a crosslinked polymeric material housing live microorganisms where the microbial solution and crosslinking agent solution are each sprayed through one of the innermost two channels of the co-axial nozzle and an atomizing gas is sprayed through the outermost channel. In a specific embodiment, the polymeric material is alginate, and the microbial population is selected from one or more of probiotic bacteria and/or a live biotherapeutic.
    Type: Application
    Filed: February 18, 2022
    Publication date: March 7, 2024
    Inventors: Say Chye Joachim LOO, Li Ling TAN, Manish MAHOTRA
  • Publication number: 20230385569
    Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Inventors: Jian SU, Jialin ZHOU, Wei ZHUANG, Ling TAN
  • Patent number: 11742283
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 29, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kah Wee Gan, Benfu Lin, Yun Ling Tan
  • Patent number: 11610837
    Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 21, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuesong Rao, Benfu Lin, Bo Li, Chengang Feng, Yudi Setiawan, Yun Ling Tan
  • Publication number: 20220208675
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes: a memory device in back end of line (BEOL) materials; and a thin film resistor located in the BEOL materials.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Kah Wee GAN, Benfu LIN, Yun Ling TAN
  • Patent number: 11315876
    Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 26, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Yun Ling Tan, Yudi Setiawan, Siow Lee Chwa
  • Publication number: 20220093508
    Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Inventors: XUESONG RAO, BENFU LIN, BO LI, CHENGANG FENG, YUDI SETIAWAN, YUN LING TAN
  • Patent number: 11234762
    Abstract: A device for vascular denervation comprising a catheter for insertion into a vessel, at least one elongated catheter arm having alternating regions of flexible joints and rigid blocks along the at least one catheter arm, wherein each of the at least one catheter arm comprises at least one tactile sensor and at least one temperature sensor; at least one electrode and electrical circuitry disposed on each of the at least one catheter arm and at least one linkage connected to all of the elongated catheter arms. A method for batch fabricating a plurality of catheter arms for the vascular denervation device is also provided and comprises the steps of depositing a first polymer coating on a semiconductor substrate, forming metal traces on the first polymer coating, patterning and etching the substrate to the first polymer coating to create flexible joint regions.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 1, 2022
    Assignees: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, HANDOK KALOS MEDICAL
    Inventors: Ming-Yuan Cheng, Songsong Zhang, Alex Yuandong Gu, Andrew Benson Randles, Ee Lim Tan, Pushpapraj Singh, Kwan Ling Tan, Weiguo Chen, Ruiqi Lim, Ramona Damalerio, Surasit Chungpaiboonpatana, Eul Joon Park, Jung Soo Oh, Jae Hyung Park, In Hee Bae
  • Publication number: 20210257300
    Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 19, 2021
    Inventors: XUESONG RAO, YUN LING TAN, YUDI SETIAWAN, SIOW LEE CHWA