Patents by Inventor Ling Tan

Ling Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966807
    Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: April 23, 2024
    Assignee: Nanjing University of Information Science and Technology
    Inventors: Jian Su, Jialin Zhou, Wei Zhuang, Ling Tan
  • Publication number: 20240107521
    Abstract: The present disclosure provides a method in a terminal device. The method includes: receiving, from a network node, at least one of cell specific Time Division Duplex, TDD, uplink-downlink configuration information and User Equipment, UE, specific TDD uplink-downlink configuration information; and determining whether a slot is available for Physical Uplink Shared Channel, PUSCH, repetition based on the at least one of the cell specific TDD uplink-downlink configuration information and the UE specific TDD uplink-downlink configuration information.
    Type: Application
    Filed: January 11, 2022
    Publication date: March 28, 2024
    Inventors: Ling SU, Zhipeng LIN, Yuande TAN
  • Patent number: 11931256
    Abstract: Disclosed is a prosthetic heart valve, wherein the prosthetic heart valve comprises: a ring-shaped stent, comprising: a mesh structure which allows the stent to be contracted or expanded in a radial direction; and a leaflet structure, comprising a plurality of leaflets, each leaflet is attached to the stent and has a first portion disposed within the stent and a second portion being wrapped to an outer circumferential side of the proximal end of the stent. With a growth of the heart, the stent can be expanded after the prosthetic heart valve is anchored, to allow the prosthetic heart valve to operate in different states, and under at least one of the different states, each leaflet has an excessive portion freely sagging to a position away from the stent along a direction from the distal end to the proximal end, to allow the stent to form a more functional valve.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: March 19, 2024
    Assignee: SEVEN SUMMITS MEDICAL, INC.
    Inventors: Jian Tan, Ling Zhou, Kailiang Zhang, Albert Yuheng Lee
  • Patent number: 11934523
    Abstract: This document discloses a system and method for securing data files selected from a series of data files. The system comprises a transformation module, an artificial neural network (ANN), a clustering module and a backpropagation module whereby these modules are configured to identify data files that contain malware or anomalies. When such data files are detected, the system will then initiate a series of measures to identify other data files that may be similarly afflicted by the detected malware. These data files are then secured to prevent the malware from affecting a host machine and/or any storage/peripheral devices linked to the host machine.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 19, 2024
    Assignee: FLEXXON PTE. LTD.
    Inventors: Mei Ling Chan, Hong Chuan Tan
  • Publication number: 20240074984
    Abstract: The present invention relates to a method of forming polymeric microparticles housing live microorganisms, the method using the steps of (a) providing a microbial solution comprising a crosslinkable polymeric material compatible with live microorganisms; a protective agent; a microbial population; and water; and a crosslinking agent solution comprising a crosslinking agent and water; and (b) subjecting the microbial and crosslinking agent solutions to spray-drying using a co-axial nozzle configured to spray at least three fluids independently, thereby producing microparticles of a crosslinked polymeric material housing live microorganisms where the microbial solution and crosslinking agent solution are each sprayed through one of the innermost two channels of the co-axial nozzle and an atomizing gas is sprayed through the outermost channel. In a specific embodiment, the polymeric material is alginate, and the microbial population is selected from one or more of probiotic bacteria and/or a live biotherapeutic.
    Type: Application
    Filed: February 18, 2022
    Publication date: March 7, 2024
    Inventors: Say Chye Joachim LOO, Li Ling TAN, Manish MAHOTRA
  • Publication number: 20240071869
    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Publication number: 20240071881
    Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Wei Yu, Kelvin Tan Aik Boo
  • Publication number: 20240071980
    Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240071990
    Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240074048
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Hong Wan Ng, Kelvin Tan Aik Boo, Seng Kim Ye, See Hiong Leow
  • Publication number: 20230385569
    Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Inventors: Jian SU, Jialin ZHOU, Wei ZHUANG, Ling TAN
  • Patent number: 11742283
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 29, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kah Wee Gan, Benfu Lin, Yun Ling Tan
  • Patent number: 11610837
    Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 21, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuesong Rao, Benfu Lin, Bo Li, Chengang Feng, Yudi Setiawan, Yun Ling Tan
  • Publication number: 20220208675
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes: a memory device in back end of line (BEOL) materials; and a thin film resistor located in the BEOL materials.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Kah Wee GAN, Benfu LIN, Yun Ling TAN
  • Patent number: 11315876
    Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 26, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Yun Ling Tan, Yudi Setiawan, Siow Lee Chwa
  • Publication number: 20220093508
    Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Inventors: XUESONG RAO, BENFU LIN, BO LI, CHENGANG FENG, YUDI SETIAWAN, YUN LING TAN
  • Patent number: 11234762
    Abstract: A device for vascular denervation comprising a catheter for insertion into a vessel, at least one elongated catheter arm having alternating regions of flexible joints and rigid blocks along the at least one catheter arm, wherein each of the at least one catheter arm comprises at least one tactile sensor and at least one temperature sensor; at least one electrode and electrical circuitry disposed on each of the at least one catheter arm and at least one linkage connected to all of the elongated catheter arms. A method for batch fabricating a plurality of catheter arms for the vascular denervation device is also provided and comprises the steps of depositing a first polymer coating on a semiconductor substrate, forming metal traces on the first polymer coating, patterning and etching the substrate to the first polymer coating to create flexible joint regions.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 1, 2022
    Assignees: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, HANDOK KALOS MEDICAL
    Inventors: Ming-Yuan Cheng, Songsong Zhang, Alex Yuandong Gu, Andrew Benson Randles, Ee Lim Tan, Pushpapraj Singh, Kwan Ling Tan, Weiguo Chen, Ruiqi Lim, Ramona Damalerio, Surasit Chungpaiboonpatana, Eul Joon Park, Jung Soo Oh, Jae Hyung Park, In Hee Bae
  • Publication number: 20210257300
    Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 19, 2021
    Inventors: XUESONG RAO, YUN LING TAN, YUDI SETIAWAN, SIOW LEE CHWA
  • Patent number: 10784332
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Yun Ling Tan, Kai Hung Alex See, Lulu Peng, Donald Ray Disney
  • Patent number: D885405
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 26, 2020
    Inventor: Ling Tan