Abstract: The present disclosure relates to a method for stochastic inspections on power grid lines based on unmanned aerial vehicle-assisted edge computing. According to the method, a stochastic distributed inspection unmanned aerial vehicle is adopted to acquire video images on a target power grid area, which can reduce funds and time costs of inspections. With assistance of superior unmanned aerial vehicle, a goal is to minimize energy consumption of an unmanned aerial vehicle system and extend operation time of the unmanned aerial vehicles under same payload conditions, while processing video image data collected from the inspection unmanned aerial vehicles. The near-far effect generated by communications between mobile unmanned aerial vehicles is eliminated by introducing a NOMA, and position coordinates, system resource allocations and task offload decision schemes are solved by using a method of combining a DDPG algorithm in a Deep reinforcement learning with a genetic algorithm.

Abstract: The present disclosure relates to a method for stochastic inspections on power grid lines based on unmanned aerial vehicle-assisted edge computing. According to the method, a stochastic distributed inspection unmanned aerial vehicle is adopted to acquire video images on a target power grid area, which can reduce funds and time costs of inspections. With assistance of superior unmanned aerial vehicle, a goal is to minimize energy consumption of an unmanned aerial vehicle system and extend operation time of the unmanned aerial vehicles under same payload conditions, while processing video image data collected from the inspection unmanned aerial vehicles. The near-far effect generated by communications between mobile unmanned aerial vehicles is eliminated by introducing a NOMA, and position coordinates, system resource allocations and task offload decision schemes are solved by using a method of combining a DDPG algorithm in a Deep reinforcement learning with a genetic algorithm.

Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.

Abstract: The present invention relates to a method of forming polymeric microparticles housing live microorganisms, the method using the steps of (a) providing a microbial solution comprising a crosslinkable polymeric material compatible with live microorganisms; a protective agent; a microbial population; and water; and a crosslinking agent solution comprising a crosslinking agent and water; and (b) subjecting the microbial and crosslinking agent solutions to spray-drying using a co-axial nozzle configured to spray at least three fluids independently, thereby producing microparticles of a crosslinked polymeric material housing live microorganisms where the microbial solution and crosslinking agent solution are each sprayed through one of the innermost two channels of the co-axial nozzle and an atomizing gas is sprayed through the outermost channel. In a specific embodiment, the polymeric material is alginate, and the microbial population is selected from one or more of probiotic bacteria and/or a live biotherapeutic.

Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.

Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes: a memory device in back end of line (BEOL) materials; and a thin film resistor located in the BEOL materials.

Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

Abstract: A device for vascular denervation comprising a catheter for insertion into a vessel, at least one elongated catheter arm having alternating regions of flexible joints and rigid blocks along the at least one catheter arm, wherein each of the at least one catheter arm comprises at least one tactile sensor and at least one temperature sensor; at least one electrode and electrical circuitry disposed on each of the at least one catheter arm and at least one linkage connected to all of the elongated catheter arms. A method for batch fabricating a plurality of catheter arms for the vascular denervation device is also provided and comprises the steps of depositing a first polymer coating on a semiconductor substrate, forming metal traces on the first polymer coating, patterning and etching the substrate to the first polymer coating to create flexible joint regions.

Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Abstract: An apparatus, device, and charging system are provided. The apparatus comprises a primary stationary receive coil and a secondary rotatable receive coil, the primary stationary receive coil being electronically coupled to the secondary rotatable receive coil. The secondary rotatable receive coil provides a charge mode position when rotated in a same plane as the primary stationary receive coil. The secondary rotatable receive coil provides non-charge mode position when retracted back against the primary stationary receive coil. The coils may be coupled is series and or parallel configurations. The primary stationary receive coil may be integrated within or appended to a housing. The secondary rotatable receive coil may be integrated within or coupled to a rotatable clip coupled to the housing. Rotation of the clip extends a charging configuration with which to charge the primary stationary receive coil and the secondary rotatable receive coil.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.