Abstract: An in-ear earphone including a housing having a first end for receiving a cable, and a second end which is placed in a concha of a user. Provided at the second end is a sealing unit which seals off an outer end of the ear canal in the region of the concha. The sealing unit has a first and a second end. The sealing unit further has a portion between the first and second ends, wherein both the inside diameter and also the outside diameter of the second end increase in the direction of the second end.

Abstract: A method of monitoring a reformer unit is disclosed. The method includes analyzing at least one of the feedstock and the product stream. The analyzing includes performing a detailed hydrocarbon analysis of at least one of the feedstock and the product stream. The method further includes obtaining a one-dimensional output from the detailed hydrocarbon analysis and adjusting the one-dimensional output to produce a multi-dimensional equivalent output. Adjusting the one-dimensional output includes applying an appropriate correlation matrix to the one-dimensional output to produce the multi-dimensional equivalent output. The appropriate correlation matrix is selected based upon the characteristics of the feedstock and the particular refinery unit.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.

Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

Abstract: A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.

Abstract: A composition suitable for forming a paint marking on a roadway comprises a polyfunctional acrylate having at least four acrylate groups, an epoxy component and a polyfunctional amine. The polyfunctional acrylate reacts with the polyfunctional amine to form an adduct with secondary amine groups. The secondary amine reacts with the epoxy component to yield a chemically high crosslinked material having a no track time of less than about five minutes.

Abstract: An in-ear earphone including a housing having a first end for receiving a cable, and a second end which is placed in a concha of a user. Provided at the second end is a sealing unit which seals off an outer end of the ear canal in the region of the concha. The sealing unit has a first and a second end. The sealing unit further has a portion between the first and second ends, wherein both the inside diameter and also the outside diameter of the second end increase in the direction of the second end.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: A method of monitoring a reformer unit is disclosed. The method includes analyzing at least one of the feedstock and the product stream. The analyzing includes performing a detailed hydrocarbon analysis of at least one of the feedstock and the product stream. The method further includes obtaining a one-dimensional output from the detailed hydrocarbon analysis and adjusting the one-dimensional output to produce a multi-dimensional equivalent output. Adjusting the one-dimensional output includes applying an appropriate correlation matrix to the one-dimensional output to produce the multi-dimensional equivalent output. The appropriate correlation matrix is selected based upon the characteristics of the feedstock and the particular refinery unit.

Abstract: An adjustable print media path system and method are disclosed. In one form, the print media path system incorporates a frame and a guide member that is moveably coupled to the frame between a cartridge position and an external media position. Inserting print media into the receptacle moves the guide member between the external media position and the cartridge position, thereby adjusting the print media path.

Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

Abstract: For forming a nickel mold, a metal and a corresponding etchant are selected such that the etchant selectively etches the metal over nickel. The metal is sputtered onto a surface of a template having nano-structures to form a sacrificial layer covering the nano-structures. Nickel is electroplated onto the sacrificial layer to form a nickel mold, but leaving a portion of the sacrificial layer exposed. The sacrificial layer is contacted with the etchant through the exposed portion of the sacrificial layer to etch away the sacrificial layer until the nickel mold is separated from the template. Subsequently, the nickel mold may be replicated or scaled-up to produce a replicate mold by electroplating, where the replicate mold has nano-structures that match the nano-structures on the template. The metal may be copper.

Abstract: A composition suitable for forming a paint marking on a roadway comprises a secondary amine adduct having at least two secondary amine groups, an amine diluent and a polyisocyanate. The secondary amine adduct and the amine diluent react with the polyisocyanate to yield a chemically high crosslinked material having a no track time of about two minutes.

Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.