Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Abstract: An apparatus, device, and charging system are provided. The apparatus comprises a primary stationary receive coil and a secondary rotatable receive coil, the primary stationary receive coil being electronically coupled to the secondary rotatable receive coil. The secondary rotatable receive coil provides a charge mode position when rotated in a same plane as the primary stationary receive coil. The secondary rotatable receive coil provides non-charge mode position when retracted back against the primary stationary receive coil. The coils may be coupled is series and or parallel configurations. The primary stationary receive coil may be integrated within or appended to a housing. The secondary rotatable receive coil may be integrated within or coupled to a rotatable clip coupled to the housing. Rotation of the clip extends a charging configuration with which to charge the primary stationary receive coil and the secondary rotatable receive coil.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

Abstract: An apparatus, device, and charging system are provided. The apparatus comprises a primary stationary receive coil and a secondary rotatable receive coil, the primary stationary receive coil being electronically coupled to the secondary rotatable receive coil. The secondary rotatable receive coil provides a charge mode position when rotated in a same plane as the primary stationary receive coil. The secondary rotatable receive coil provides non-charge mode position when retracted back against the primary stationary receive coil. The coils may be coupled is series and or parallel configurations. The primary stationary receive coil may be integrated within or appended to a housing. The secondary rotatable receive coil may be integrated within or coupled to a rotatable clip coupled to the housing. Rotation of the clip extends a charging configuration with which to charge the primary stationary receive coil and the secondary rotatable receive coil.

Abstract: During processing of job documents in a document processing workflow, execution of the workflow is stopped at a previously defined first sequentially processed node until no more of the job documents can be directed to the first sequentially processed node by the workflow. Then, the job documents that have been stopped at the first sequentially processed node are arranged in a document order, and the sequentially processed nodes are executed for each of the multiple job documents that have been stopped (and such job documents are processed one at a time through the sequentially processed nodes). Thus, execution waits until an immediately previous one of the job documents (in the document order) has finished processing at a previously defined last sequentially processed node before starting processing an immediately subsequent one of the job documents (in the document order) at the first sequentially processed node.

Abstract: A device for vascular denervation comprising a catheter for insertion into a vessel, at least one elongated catheter arm having alternating regions of flexible joints and rigid blocks along the at least one catheter arm, wherein each of the at least one catheter arm comprises at least one tactile sensor and at least one temperature sensor; at least one electrode and electrical circuitry disposed on each of the at least one catheter arm and at least one linkage connected to all of the elongated catheter arms. A method for batch fabricating a plurality of catheter arms for the vascular denervation device is also provided and comprises the steps of depositing a first polymer coating on a semiconductor substrate, forming metal traces on the first polymer coating, patterning and etching the substrate to the first polymer coating to create flexible joint regions.

Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

Abstract: The present disclosure relates to a method of forming a metallic layer having pores extending therethrough, the method comprising the steps of: (a) contacting a cathode substrate with an electrolyte solution comprising at least one cation; reducing the cation to deposit the metallic layer on a surface of the cathode substrate; and (c) generating a plurality of non-conductive regions on the cathode substrate surface during reducing step (b); wherein the deposition of the metallic layer is substantially prevented on the non-conductive regions on the cathode substrate surface to thereby form pores extending through the deposited metallic layer. The present disclosure further provides a metallic porous membrane fabricated by the disclosed process.

Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Abstract: During processing of job documents in a document processing workflow, execution of the workflow is stopped at a previously defined first sequentially processed node until no more of the job documents can be directed to the first sequentially processed node by the workflow. Then, the job documents that have been stopped at the first sequentially processed node are arranged in a document order, and the sequentially processed nodes are executed for each of the multiple job documents that have been stopped (and such job documents are processed one at a time through the sequentially processed nodes). Thus, execution waits until an immediately previous one of the job documents (in the document order) has finished processing at a previously defined last sequentially processed node before starting processing an immediately subsequent one of the job documents (in the document order) at the first sequentially processed node.

Abstract: A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: The present disclosure relates to a method of forming a metallic layer having pores extending therethrough, the method comprising the steps of: (a) contacting a cathode substrate with an electrolyte solution comprising at least one cation; reducing the cation to deposit the metallic layer on a surface of the cathode substrate; and (c) generating a plurality of non-conductive regions on the cathode substrate surface during reducing step (b); wherein the deposition of the metallic layer is substantially prevented on the non-conductive regions on the cathode substrate surface to thereby form pores extending through the deposited metallic layer. The present disclosure further provides a metallic porous membrane fabricated by the disclosed process.

Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Abstract: For forming a nickel mold, a metal and a corresponding etchant are selected such that the etchant selectively etches the metal over nickel. The metal is sputtered onto a surface of a template having nano-structures to form a sacrificial layer covering the nano-structures. Nickel is electroplated onto the sacrificial layer to form a nickel mold, but leaving a portion of the sacrificial layer exposed. The sacrificial layer is contacted with the etchant through the exposed portion of the sacrificial layer to etch away the sacrificial layer until the nickel mold is separated from the template. Subsequently, the nickel mold may be replicated or scaled-up to produce a replicate mold by electroplating, where the replicate mold has nano-structures that match the nano-structures on the template. The metal may be copper.

Abstract: A Multiple Registration Protocol (MRP) advertisement control capability is provided. A method includes receiving an MRP advertisement at a device configured as an interface between a core domain and a local domain and determining handling of the MRP advertisement at the device using at least one MRP policy stored on the device. The core domain may be a Provider Backbone Bridging (PBB) network or other suitable core network. The local domain may be one of a PBB network, a Provider Bridging Network (PBN), a Metropolitan Area Network (MAN), and the like. In one case, when the MRP advertisement is associated with a local service of the local domain, the MRP policy indicates that the MRP advertisement is not to be forwarded via the core domain.