Abstract: In accordance with embodiments of the present disclosure, systems and methods may include an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The systems and methods may also include a predriver circuit coupled to the input and a gate terminal of the first switch device, the predriver circuit configured to drive an input voltage signal to the gate terminal of the first switch device and configured to select an effective impedance of the gate terminal of the first switch device based on the input.

Abstract: A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier.

Abstract: An asymmetric modulation scheme may be used to drive two output nodes coupled to a load. The asymmetric modulation scheme may be one-sided such that the switching rate of a first output node is lower than the switching rate of a second output node. The first output node may be switched only to change a direction of current between the first output node and the second output node, while the second output node is switched to convey the information of an input signal. The asymmetric modulation scheme may be used to drive a speaker to reduce noise at the first output node to improve accuracy of current monitoring through the speaker by a current monitor coupled at the first output node.

Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.

Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.

Abstract: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.

Abstract: A single integrated circuit includes a single boost converter, a first circuit, a second circuit, and a controller. The single boost converter supplies power to the first and second circuits. The controller receives an operational mode signal and in response to the operational mode signal, drives the single boost converter to respectively provide power to the first and second circuits. When the first and second circuits are simultaneously active, the controller manages an operation of the first circuit so that proper operation of the second circuit is maintained. The first circuit may be an LED flash driver, and the second circuit may be an audio amplifier, such as a Class-D audio amplifier. The controller manages an operation of the audio amplifier so that a sufficient amount of current is supplied to the LED flash driver for proper operation of the LED flash driver.

Abstract: A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier.

Abstract: In accordance with these and other embodiments of the present disclosure, a system and method include supplying, by a single boost converter, power to a first circuit that provides a circuit operation and power to a second circuit that provides another circuit operation. The system and method also include receiving, by a controller coupled to the single boost controller, an operating condition signal indicative of at least one of: (i) a power delivered by the single boost converter, and (ii) a temperature of the single integrated circuit. The system and method further include allocating, by the controller, power deliverable by the single boost converter between the first circuit and second circuit in response to the operating condition signal.

Abstract: Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

Abstract: In accordance with embodiments of the present disclosure, an apparatus may include an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and a predriver circuit coupled to the input and a gate terminal of the at least one driver device, the predriver circuit for driving an input voltage signal to the gate terminal and configured to select an effective impedance of the gate terminal based on the input for indicating the output load current. In accordance with these and other embodiments of the disclosure, a method may include receiving an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and selecting an effective impedance of a gate terminal of the at least one driver device based on the input for indicating the output load current.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: Various embodiments enable a group of devices to be logically grouped together in what is referred to as a “device circle.” The devices in a device circle can be bound through static and dynamic bindings. In at least some embodiments, the device circle serves as a single abstract entity that does not necessarily expose its individual constituent devices. As such, communication and other functionality can take place with the device circle in a manner that does not divulge the identities, capabilities, or roles of the individual devices that make up the device circle.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a variable offset pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

Abstract: In accordance with embodiments of the present disclosure, systems and methods may include a switch coupled at its gate terminal to an input signal voltage, the input signal voltage for controlling a gate voltage of a gate terminal of a driver device coupled at its non-gate terminals between a rail voltage and an output node. The systems and methods may also include a diode having a first terminal and a second terminal, the diode coupled to a non-gate terminal of the switch such that when the switch is enabled, the first terminal is electrically coupled to the gate terminal of the driver device and the second terminal is electrically coupled to the output node.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.