Abstract: Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

Abstract: In accordance with these and other embodiments of the present disclosure, an apparatus and a method may include receiving a first input configured to indicate an output voltage of an output node of a switched output stage comprising a pull-down driver device coupled at its non-gate terminals between a ground voltage and the output node and a pull-up driver device coupled at its non-gate terminals between a supply voltage and the output node. The method may also include receiving a second input configured to indicate a gate voltage of a gate terminal of a first one of the pull-up driver device and the pull-down driver device. The method may further include detecting direction of an output current flowing into or out of the output node based on the first input and the second input.

Abstract: An asymmetric modulation scheme may be used to drive two output nodes coupled to a load. The asymmetric modulation scheme may be one-sided such that the switching rate of a first output node is lower than the switching rate of a second output node. The first output node may be switched only to change a direction of current between the first output node and the second output node, while the second output node is switched to convey the information of an input signal. The asymmetric modulation scheme may be used to drive a speaker to reduce noise at the first output node to improve accuracy of current monitoring through the speaker by a current monitor coupled at the first output node.

Abstract: In accordance with embodiments of the present disclosure, systems and methods may include a switch coupled at its gate terminal to an input signal voltage, the input signal voltage for controlling a gate voltage of a gate terminal of a driver device coupled at its non-gate terminals between a rail voltage and an output node. The systems and methods may also include a diode having a first terminal and a second terminal, the diode coupled to a non-gate terminal of the switch such that when the switch is enabled, the first terminal is electrically coupled to the gate terminal of the driver device and the second terminal is electrically coupled to the output node.

Abstract: In accordance with these and other embodiments of the present disclosure, an apparatus and a method may include receiving a first input configured to indicate an output voltage of an output node of a switched output stage comprising a pull-down driver device coupled at its non-gate terminals between a ground voltage and the output node and a pull-up driver device coupled at its non-gate terminals between a supply voltage and the output node. The method may also include receiving a second input configured to indicate a gate voltage of a gate terminal of a first one of the pull-up driver device and the pull-down driver device. The method may further include detecting direction of an output current flowing into or out of the output node based on the first input and the second input.

Abstract: In accordance with embodiments of the present disclosure, systems and methods may include an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The systems and methods may also include a predriver circuit coupled to the input and a gate terminal of the first switch device, the predriver circuit configured to drive an input voltage signal to the gate terminal of the first switch device and configured to select an effective impedance of the gate terminal of the first switch device based on the input.

Abstract: A high level programming language provides an extensible set of transformations for use on indexable types in a data parallel processing environment. A compiler for the language implements each transformation as a map from indexable types to allow each transformation to be applied to other transformations. At compile time, the compiler identifies sequences of the transformations on each indexable type in data parallel source code and generates data parallel executable code to implement the sequences as a combined operation at runtime using the transformation maps. The compiler also incorporates optimizations that are based on the sequences of transformations into the data parallel executable code.

Abstract: A compile environment is provided in a computer system that allows programmers to program both CPUs and data parallel devices (e.g., GPUs) using a high level general purpose programming language that has data parallel (DP) extensions. A compilation process translates modular DP code written in the general purpose language into DP device source code in a high level DP device programming language using a set of binding descriptors for the DP device source code. A binder generates a single, self-contained DP device source code unit from the set of binding descriptors. A DP device compiler generates a DP device executable for execution on one or more data parallel devices from the DP device source code unit.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.

Abstract: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into High Level Shader Language (“HLSL”) source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

Abstract: A single integrated circuit includes a single boost converter, a first circuit, a second circuit, and a controller. The single boost converter supplies power to the first and second circuits. The controller receives an operational mode signal and in response to the operational mode signal, drives the single boost converter to respectively provide power to the first and second circuits. When the first and second circuits are simultaneously active, the controller manages an operation of the first circuit so that proper operation of the second circuit is maintained. The first circuit may be an LED flash driver, and the second circuit may be an audio amplifier, such as a Class-D audio amplifier. The controller manages an operation of the audio amplifier so that a sufficient amount of current is supplied to the LED flash driver for proper operation of the LED flash driver.

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation.

Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.

Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into HLSL source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.