Abstract: An audio switching power amplifier having an output pulse voltage selected in conformity with an indication of the output signal amplitude provides lower electromagnetic interference (EMI) in class-D amplifier implementations, in particular, in inductor-less designs. The output pulse voltage may be selected by providing multiple switching circuits, such as half or fully bridge switches, with each switching circuit connected to a different power supply. One of the switching circuits is activated by the switching controller, while the others are disabled, providing selection of the output pulse voltage. Selection of a lower pulse voltage, when the maximum voltage is not required, reduces the generated EMI. The switching frequency of the class-D amplifier may also be controlled in conformity with the output signal amplitude, so that at higher output levels a lower switching rate is selected, reducing the generated EMI.

Abstract: A high level programming language provides an extensible set of transformations for use on indexable types in a data parallel processing environment. A compiler for the language implements each transformation as a map from indexable types to allow each transformation to be applied to other transformations. At compile time, the compiler identifies sequences of the transformations on each indexable type in data parallel source code and generates data parallel executable code to implement the sequences as a combined operation at runtime using the transformation maps. The compiler also incorporates optimizations that are based on the sequences of transformations into the data parallel executable code.

Abstract: Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During execution of the executable program, data is exchanged between non-data parallel (non-DP) capable hardware and DP capable hardware for the invocation of data parallel functions.

Abstract: A compile environment is provided in a computer system that allows programmers to program both CPUs and data parallel devices (e.g., GPUs) using a high level general purpose programming language that has data parallel (DP) extensions. A compilation process translates modular DP code written in the general purpose language into DP device source code in a high level DP device programming language using a set of binding descriptors for the DP device source code. A binder generates a single, self-contained DP device source code unit from the set of binding descriptors. A DP device compiler generates a DP device executable for execution on one or more data parallel devices from the DP device source code unit.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.

Abstract: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.

Abstract: Various technologies and techniques are disclosed for handling exceptions in sequential statements that are executed in parallel. A transactional memory system is provided with a contention manager. The contention manager is responsible for managing exceptions that occur within statements that were designed to be executed in an original sequential order, and that were transformed into ordered transactions for speculative execution in parallel. The contention manager ensures that any exceptions that are thrown from one or more speculatively executed blocks while the statements are being executed speculatively in parallel are handled in the original sequential order.

Abstract: A data processing system including an input data port for receiving input data samples asynchronous to a native clock signal and having an input sample rate, a first sample rate converter for converting the data samples from the input sample rate to a sample rate synchronous with a rate of the native clock signal, and a data converter for converting data samples output from the first sample rate converter to another format. An analog to digital converter converts an analog signal into output data samples with a sample rate synchronous with the rate of the native clock signal, and a second sample rate converter converts the sample rate of the output data samples from the sample rate synchronous with the rate of the native clock signal to an output sample rate such that output data samples are asynchronous to the native clock signal.

Abstract: Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation.

Abstract: Various technologies and techniques are disclosed for applying ordering to transactions in a software transactional memory system. A software transactional memory system is provided with a feature to allow a pre-determined commit order to be specified for a plurality of transactions. The pre-determined commit order is used at runtime to aid in determining an order in which to commit the transactions in the software transactional memory system. A contention management process is invoked when a conflict occurs between a first transaction and a second transaction. The pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed.

Abstract: A pulse width modulation system including a pulse width modulation stage for generating a pulse width modulated signal in response to an input signal and an other pulse width modulation stage for generating an other pulse width modulated signal in response to an other input signal. Additional circuitry ensures that transitions of the pulse width modulated signal and the other pulse width modulated signal are spaced in time by a selected amount for small levels of the input signal.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: A thermal overload protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier output is disabled in response to a thermal overload condition. Upon detection of a thermal overload condition, rather than immediately disabling the switching power output stage, the switching power output stage is driven toward a fifty-percent duty cycle of operation for a predetermined time period so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise may cause latch-up within the integrated circuit when the switching power output stage is disabled. After the time period has elapsed, the switching power output stage is disabled. Alternatively, the current through the inductive load is measured and the switching power stage is disabled after the magnitude of the current has fallen below a threshold.

Abstract: A protection circuit and method for protecting switching power amplifier circuits during reset provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier is reset. Upon receipt of a reset indication, rather than immediately disabling the switching power output stage, the switching power output stage is driven toward a fifty-percent duty cycle of operation for a time period so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise may cause latch-up of the output stage when the switching power output stage is disabled. After the time period has elapsed, the switching power output stage is disabled. Alternatively, the current through the inductive load is measured and the switching power stage is disabled after the magnitude of the current has fallen below a threshold.

Abstract: An over-current protection circuit protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when one or more transistors in the amplifier output are disabled in response to an over-current condition. Upon detection of an over-current condition, the transistor corresponding to the over-current conduction direction is disabled. At the same time, the transistor corresponding to the conduction direction opposite the over-current direction is enabled for a predetermined time period, or until the magnitude of the load current has dropped, so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise cause latch-up and consequent destruction of the output stage when the switching power output stage is disabled. After the predetermined time period has elapsed or the load current has dropped below a threshold, the entire output stage is disabled.

Abstract: Various technologies and techniques are disclosed for applying ordering to transactions in a software transactional memory system. A software transactional memory system is provided with a feature to allow a pre-determined commit order to be specified for a plurality of transactions. The pre-determined commit order is used at runtime to aid in determining an order in which to commit the transactions in the software transactional memory system. A contention management process is invoked when a conflict occurs between a first transaction and a second transaction. The pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed.

Abstract: Various technologies and techniques are disclosed for handling exceptions in sequential statements that are executed in parallel. A transactional memory system is provided with a contention manager. The contention manager is responsible for managing exceptions that occur within statements that were designed to be executed in an original sequential order, and that were transformed into ordered transactions for speculative execution in parallel. The contention manager ensures that any exceptions that are thrown from one or more speculatively executed blocks while the statements are being executed speculatively in parallel are handled in the original sequential order.

Abstract: A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.

Abstract: A pre-charge apparatus and method for controlling startup transients in a capacitively-coupled switching power stage provide lower cost and improved startup transient performance in Class D amplifiers, as well as in other AC power converter applications. A charging source is activated at startup to control the charging of an external capacitor from a single power supply rail to an operating point voltage equal to the average DC output of the switching circuit, while a control circuit disables the output power stage of the switching converter. The current source may be a constant-current source and/or may be controlled via feedback from the voltage or current at the output terminal of the converter to taper the current level to more accurately control the charging. A discharge circuit can also be provided to discharge the output terminal to an opposite power supply rail before commencing the controlled charging.