Abstract: A compile environment is provided in a computer system that allows programmers to program both CPUs and data parallel devices (e.g., GPUs) using a high level general purpose programming language that has data parallel (DP) extensions. A compilation process translates modular DP code written in the general purpose language into DP device source code in a high level DP device programming language using a set of binding descriptors for the DP device source code. A binder generates a single, self-contained DP device source code unit from the set of binding descriptors. A DP device compiler generates a DP device executable for execution on one or more data parallel devices from the DP device source code unit.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.

Abstract: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into High Level Shader Language (“HLSL”) source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

Abstract: A single integrated circuit includes a single boost converter, a first circuit, a second circuit, and a controller. The single boost converter supplies power to the first and second circuits. The controller receives an operational mode signal and in response to the operational mode signal, drives the single boost converter to respectively provide power to the first and second circuits. When the first and second circuits are simultaneously active, the controller manages an operation of the first circuit so that proper operation of the second circuit is maintained. The first circuit may be an LED flash driver, and the second circuit may be an audio amplifier, such as a Class-D audio amplifier. The controller manages an operation of the audio amplifier so that a sufficient amount of current is supplied to the LED flash driver for proper operation of the LED flash driver.

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation.

Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.

Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into HLSL source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.

Abstract: An audio switching power amplifier having an output pulse voltage selected in conformity with an indication of the output signal amplitude provides lower electromagnetic interference (EMI) in class-D amplifier implementations, in particular, in inductor-less designs. The output pulse voltage may be selected by providing multiple switching circuits, such as half or fully bridge switches, with each switching circuit connected to a different power supply. One of the switching circuits is activated by the switching controller, while the others are disabled, providing selection of the output pulse voltage. Selection of a lower pulse voltage, when the maximum voltage is not required, reduces the generated EMI. The switching frequency of the class-D amplifier may also be controlled in conformity with the output signal amplitude, so that at higher output levels a lower switching rate is selected, reducing the generated EMI.

Abstract: A high level programming language provides an extensible set of transformations for use on indexable types in a data parallel processing environment. A compiler for the language implements each transformation as a map from indexable types to allow each transformation to be applied to other transformations. At compile time, the compiler identifies sequences of the transformations on each indexable type in data parallel source code and generates data parallel executable code to implement the sequences as a combined operation at runtime using the transformation maps. The compiler also incorporates optimizations that are based on the sequences of transformations into the data parallel executable code.

Abstract: Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During execution of the executable program, data is exchanged between non-data parallel (non-DP) capable hardware and DP capable hardware for the invocation of data parallel functions.

Abstract: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.

Abstract: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: A compile environment is provided in a computer system that allows programmers to program both CPUs and data parallel devices (e.g., GPUs) using a high level general purpose programming language that has data parallel (DP) extensions. A compilation process translates modular DP code written in the general purpose language into DP device source code in a high level DP device programming language using a set of binding descriptors for the DP device source code. A binder generates a single, self-contained DP device source code unit from the set of binding descriptors. A DP device compiler generates a DP device executable for execution on one or more data parallel devices from the DP device source code unit.