Abstract: A high-formability, super-high-strength, hot-dip galvanized steel plate, the chemical composition of which comprises, based on weight percentage, C: 0.15-0.25 wt %, Si: 1.00-2.00 wt %, Mn: 1.50-3.00 wt %, P?0.015 wt %, S?0.012 wt %, Al: 0.03-0.06 wt %, N?0.008 wt %, and the balance of iron and unavoidable impurities. The room temperature structure of the steel plate comprises 10-30% ferrite, 60-80% martensite and 5-15% residual austenite. The steel plate has a yield strength of 600-900 MPa, a tensile strength of 980-1200 MPa, and an elongation of 15-22%. Through an appropriate composition design, a super-high-strength, cold rolled, hot-dip galvanized steel plate is manufactured by continuous annealing, wherein no expensive alloy elements are added; instead, remarkable increase of strength along with good plasticity can be realized just by appropriate augment of Si, Mn contents in combination with suitable processes of annealing and furnace atmosphere control.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A thin film transistor array substrate and a display panel are provided. A parasitic capacitor is formed from a common line and a data line, and a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a lamer resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line. Thus the displayed image bright stripes with inconsistent brightness can be avoided from appearing.

Abstract: A liquid crystal display panel and a liquid crystal display are disclosed. The liquid crystal display panel includes a color film substrate and an array substrate disposed opposite each other, wherein the array substrate includes a pixel electrode, a color resistance layer, and a thin film transistor, the color resistance layer is provided with a through hole, a drain of the thin film transistor is connected with the pixel electrode through the through hole, and a region corresponding to the through hole is provided with a spacer for separating liquid crystal molecules in the region where the through hole is located from liquid crystal molecules in a region where the electrodes are located.

Abstract: A carburized La2O3 and Lu2O3 co-doped Mo filament cathode and its fabrication method, which belongs to the technical field of rare earth-refractory metal cathodes. The rare earth oxides are La2O3 and Lu2O3, and the total concentration of rare earth oxides ranges from 2.0-5.0 wt. %. The La2O3 and Lu2O3 co-doped molybdenum oxide powers are prepared by Sol-Gel method. La2O3 and Lu2O3 co-doped Mo powers are prepared by two calcining steps. Then pressing and sintering the mixed powders to obtain the molybdenum rods; operating mechanical and heat processes of the molybdenum rods to obtain molybdenum filament. Operating electrolytic cleaning, straightening, winding modeling and cutting treatments with Mo filament to obtain the un-carburized La2O3 and Lu2O3 co-doped Mo cathode. And then carburize the filament cathode at a high temperature for a short time to obtain a cathode with high carburization degree.

Abstract: The present disclosure proposes an array substrate and a display device. The array substrate includes gate lines, data lines, and pixel units. Each pixel unit includes a main-pixel zone, a first sub-pixel zone, and a second sub-pixel zone. The voltage levels of the main-pixel zone, the first sub-pixel zone, and the sub-pixel zone are completely different owing to the effect of capacitive coupling. In this way, the present disclosure can solve the problems of image distortion in the conventional VA liquid crystal panel.

Abstract: An LCD array substrate, an LCD panel and an LCD pixel circuit are disclosed. The LCD array substrate includes: a substrate and a plurality of gate lines and data lines, wherein the gate lines and the data lines are crossed with each other to form a plurality of pixel units; each of the pixel units is provided with a pixel electrode, a first thin-film transistor, and a connecting switch controlled by the corresponding gate line; the switch is controlled to be turned on.

Abstract: An LCD array substrate, an LCD panel and an LCD pixel circuit are disclosed. The LCD array substrate includes: a substrate and a plurality of gate lines and data lines, wherein the gate lines and the data lines are crossed with each other to form a plurality of pixel units; each of the pixel units is provided with a pixel electrode, a first thin-film transistor, and a connecting switch controlled by the corresponding gate line; the switch is controlled to be turned on.

Abstract: A multi-mode multi-band power amplifier includes a controller, a wide-band amplifier channel and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives single-band or multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer includes a first segment shared by RF signals in all bands, second segments respectively special for RF signals in all bands, and a switching circuit controlled by the controller to separate RF signals subject to power amplification to the second segment in a switchable manner for multiplexed outputs.

Abstract: A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.

Abstract: A driving method of scan lines in a display panel and a driving device thereof are described. The driving method of scan lines includes the steps of dividing a plurality of frames into a first frame set and a second frame set, and turning on the scan lines of each frame in the first frame set by using a forward scan direction and turning on the scan lines in the second frame set by a backward scan direction.

Abstract: The invention includes a method including the steps of obtaining a plurality of images, each of the images in the plurality having at least one corresponding region, generating a merged image, the merged image also having the corresponding region. The step of generating includes selecting an image source from the plurality of images to source image data for the corresponding region in the merged image by comparing attributes of the corresponding regions of the plurality of images to identify the image source having preferred attributes.

Abstract: A method of manufacturing a patterned crystal structure for includes depositing an amorphous material. The amorphous material is modified such that a first portion of the amorphous thin-film layer has a first height/volume and a second portion of the amorphous thin-film layer has a second height/volume greater than the first portion. The amorphous material is annealed to induce crystallization, wherein crystallization is induced in the second portion first due to the greater height/volume of the second portion relative to the first portion to form patterned crystal structures.

Abstract: A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.

Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.

Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.

Abstract: A multi-mode multi-band power amplifier includes a controller, a wide-band amplifier channel and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives single-band or multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer includes a first segment shared by RF signals in all bands, second segments respectively special for RF signals in all bands, and a switching circuit controlled by the controller to separate RF signals subject to power amplification to the second segment in a switchable manner for multiplexed outputs.

Abstract: The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory cell arrays are the same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays. The data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays. The data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are the same.

Abstract: A collimated object is adjustable to produce collimated light propagating along different propagation directions. The plenoptic imaging system under calibration captures plenoptic images of the object adjusted to different propagation directions. The captured plenoptic images includes superpixels, each of which includes subpixels. Each subpixel captures light from a corresponding light field viewing direction. Based on the captured plenoptic images, a calibration module calculates which propagation directions map to which subpixels. The mapping defines the light field viewing directions for the subpixels. This can be used to improve processing of plenoptic images captured by the plenoptic imaging system.