Abstract: Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Abstract: The present disclosure provides a random access memory. The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory cell arrays are same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays. The data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays. The data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are same.

Abstract: A power amplifier gain switching circuit includes: a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal; an amplifier including: a bias input terminal configured to receive an external bias voltage; a signal input terminal configured to receive the first input signal; a control terminal configured to receive the control signal; and an output terminal configured to output an output signal with a gain; wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.

Abstract: There is provided herein a nanovesicle comprising a monolayer of phospholipid, porphyrin-phospholipid conjugate and a peptide encapsulating a hydrophobic core, wherein the peptide comprises an amino acid sequence capable of forming at least one amphipathic ?-helix; the porphyrin-phospholipid conjugate comprises one porphyrin, porphyrin derivative or porphyrin analog covalently attached to a lipid side chain, preferably at the sn-1 or the sn-2 position, of one phospholipid; the molar % of porphyrin-phospholipid conjugate to phospholipid is 35% or less; the nanovesicle is 35 nm in diameter or less.

Abstract: A collimated object is adjustable to produce collimated light propagating along different propagation directions. The plenoptic imaging system under calibration captures plenoptic images of the object adjusted to different propagation directions. The captured plenoptic images includes superpixels, each of which includes subpixels. Each subpixel captures light from a corresponding light field viewing direction. Based on the captured plenoptic images, a calibration module calculates which propagation directions map to which subpixels. The mapping defines the light field viewing directions for the subpixels. This can be used to improve processing of plenoptic images captured by the plenoptic imaging system.

Abstract: A multi-mode multi-band power amplifier and its circuits are provided. The power amplifier comprises a controller, a wide-band amplifier channel, and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives a single-band or a multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer comprises a first segment shared by RF signals in all bands, second segments respectively specific to RF signals in all bands, and a switching circuit controlled by the controller to separate a RF signal which is subject to power amplification to the second segment in a switchable manner for multiplexed outputs. A power amplifier output power control circuit, a gain switching circuit, and a gain attenuation circuit are also provided.

Abstract: A collimated object is adjustable to produce collimated light propagating along different propagation directions. The plenoptic imaging system under calibration captures plenoptic images of the object adjusted to different propagation directions. The captured plenoptic images includes superpixels, each of which includes subpixels. Each subpixel captures light from a corresponding light field viewing direction. Based on the captured plenoptic images, a calibration module calculates which propagation directions map to which subpixels. The mapping defines the light field viewing directions for the subpixels. This can be used to improve processing of plenoptic images captured by the plenoptic imaging system.

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

Abstract: A multi-mode multi-band power amplifier and its circuits are provided. The power amplifier comprises a controller, a wide-band amplifier channel, and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives a single-band or a multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer comprises a first segment shared by RF signals in all bands, second segments respectively specific to RF signals in all bands, and a switching circuit controlled by the controller to separate a RF signal which is subject to power amplification to the second segment in a switchable manner for multiplexed outputs. A power amplifier output power control circuit, a gain switching circuit, and a gain attenuation circuit are also provided.

Abstract: The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling.

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

Abstract: A collimated object is adjustable to produce collimated light propagating along different propagation directions. The plenoptic imaging system under calibration captures plenoptic images of the object adjusted to different propagation directions. The captured plenoptic images includes superpixels, each of which includes subpixels. Each subpixel captures light from a corresponding light field viewing direction. Based on the captured plenoptic images, a calibration module calculates which propagation directions map to which subpixels. The mapping defines the light field viewing directions for the subpixels. This can be used to improve processing of plenoptic images captured by the plenoptic imaging system.

Abstract: A plenoptic camera captures a plenoptic image of an object illuminated by a point source (preferably, collimated illumination). The plenoptic image is a sampling of the four-dimensional light field reflected from the object. The plenoptic image is made up of superpixels, each of which is made up of subpixels. Each superpixel captures light from a certain region of the object (i.e., a range of x,y spatial locations) and the subpixels within a superpixel capture light propagating within a certain range of directions (i.e., a range of u,v spatial directions). Accordingly, optical properties estimation, surface normal reconstruction, depth estimation, and three-dimensional rendering can be provided by processing only a single plenoptic image. In one approach, the plenoptic image is used to estimate the bidirectional reflectance distribution function (BRDF) of the object surface.

Abstract: The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.

Abstract: A high-formability, super-high-strength, hot-dip galvanized steel plate, the chemical composition of which comprises, based on weight percentage, C: 0.15-0.25 wt %, Si: 1.00-2.00 wt %, Mn: 1.50-3.00 wt %, P?0.015 wt %, S?0.012 wt %, Al: 0.03-0.06 wt %, N?0.008 wt %, and the balance of iron and unavoidable impurities. The room temperature structure of the steel plate comprises 10-30% ferrite, 60-80% martensite and 5-15% residual austenite. The steel plate has a yield strength of 600-900 MPa, a tensile strength of 980-1200 MPa, and an elongation of 15-22%. Through an appropriate composition design, a super-high-strength, cold rolled, hot-dip galvanized steel plate is manufactured by continuous annealing, wherein no expensive alloy elements are added; instead, remarkable increase of strength along with good plasticity can be realized just by appropriate augment of Si, Mn contents in combination with suitable processes of annealing and furnace atmosphere control.

Abstract: The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first N-type transistor, a first P-type transistor, a second N-type transistor and a second P-type transistor, in which an absolute value of a threshold voltage of the first N-type transistor is greater than an absolute value of a threshold voltage of the second N-type transistor, and an absolute value of a threshold voltage of the first P-type transistor is greater than an absolute value of a threshold voltage of the second P-type transistor. The random access memory, including: two identical memory cell arrays including the cell structure with four transistors, a data write circuit and a data read circuit, by using Two Modular Redundancy harden method, and thus reading correctly and avoiding the mistake reversal caused by the single event upset effect.

Abstract: Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Abstract: A report creation method, system, and device are described, and the method includes that: abstraction processing is performed on a data table in a database, and an Abstract Data Record (ADR) model is created; a report template is created according to the ADR model, and the report template is stored; and the created report template is called, a report query operation is executed, and report data obtained by querying is displayed. Through the disclosure, a user can create a complicated report template quickly, without involving a complicated secondary development process and writing a secondary development script.

Abstract: A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.