Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

Abstract: A computing system having a host system and a memory sub-system connected to the host system. The memory sub-system is configurable to be prevented from selecting victim reclaim units for garbage collection. The host system is configured to identify a first reclaim unit having residual valid data, and perform operations to cause the residual valid data to be invalidated in the first reclaim unit. The memory sub-system is configured to erase the first reclaim unit in response to a determination that no valid data remains in the first reclaim unit.

Abstract: A host system configured to identify a victim reclaim unit, determine a logical address having a storage space implemented in the victim reclaim unit, and communicate to a memory sub-system a garbage collection request identifying the logical address. In response, the memory sub-system determines, based on a logical to physical address map, the victim reclaim unit hosting data at the logical address, and entering the victim reclaim unit into a garbage collection queue. The memory sub-system is to perform garbage collection on reclaim units in an order identified by the garbage collection queue to prioritize reclaim units identified by the host system over reclaim units identified by the memory sub-system.

Abstract: A computing device having a host system connected to a memory sub-system. The host system can: select a victim reclaim unit; identify, among the plurality of storage space tenants, a first storage space tenant having valid data remaining in the victim reclaim unit; determine, based on a current scheme of allocating resources to the plurality of storage space tenants in the host system, an estimate of a time for the first storage space tenant to complete operations to invalidate the data in the victim reclaim unit; determine, based on the estimate, that completion of the operations is to occur after an indicator of usage level of storage resources in the memory sub-system reaches a condition; and change the current scheme to a modified scheme to reduce the estimate of the time.

Abstract: A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.

Abstract: A memory sub-system, having: non-volatile memory cells configured as a plurality of reclaim units according to a technique of flexible direct placement (FDP); and a controller configured to postpone garbage collection until an indicator of usage level of storage resources in the memory sub-system reaches a first level. The controller is further configured to receive, from a host system, a request configured to cause the controller to further postpone garbage collection even after the indicator reaches the first level.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller or processing device of a host system adds an entry to a local shared work queue of the host system. The entry includes an NVMe command to be executed by the SSD. The entry also includes an address for a shared work queue of the SSD. The controller or processing device writes the command to the shared work queue of the SSD using a PCIe memory write. The command is then executed by the SSD.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, a memory sub-system (e.g., SSD) includes: at least one non-volatile memory device (e.g., flash memory); and at least one controller configured to: provide access to at least one shared work queue by exposing a portion of memory to a host system (e.g., GPU); receive, in the shared work queue, a command from the host system (e.g., NVMe command over PCIe fabric); and in response to receiving the command, copy the command to an internal command queue (e.g., queue of the SSD) for execution to access the non-volatile memory device according to an operation (e.g., read/write) identified in the command.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host/processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host/processor can send a command to enable/disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., CPU). Each command specifies an address space identifier (e.g., PASID). In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. The address space identifier is used (e.g., by a DMA engine) when performing a data transfer as part of the operation.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes an NVMe command to the SSD using a PCIe transaction layer packet. The command is written using either a deferred memory write or a memory write according to the PCIe standard. The command is written to the SSD either directly or via a local shared work queue of the host system.

Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is reconfigured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., GPU). Each command specifies an address for a completion record. In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. Then, the controller writes the completion record to a location in main memory of the host system at the address.

Abstract: A host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. The request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. The request can be implemented via a store instruction, a write command, or another command having another command identifier.

Abstract: An input/output (I/O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to establish a network connection to a cryptocurrency network, receive a proof of space challenge, and generate a response to the challenge using a plot stored in the memory cells.

Abstract: Various embodiments provide for performing one or more data read-ahead operations on a memory system based on a read size and a queue identifier of a read request. In particular, a memory system of some embodiments is configured to perform at least one read-ahead operation when an individual read request, received from a host system in association with a queue identifier, has a read size equal to a maximum data transfer size (MDTS) of the memory system.

Abstract: A memory sub-system having: a random access memory; a storage medium accessible to a host system using commands communicated via a plurality of submission queues to the memory sub-system; and a circuit configured to allocate, from the random access memory, one or more buffers that are associated respectively with one or more submission queues among the plurality of submission queues. The memory sub-system can: load data from the storage medium of the memory sub-system to a first buffer among the one or more buffers; retrieve, from a first submission queue associated with the first buffer among the plurality of the submission queues, a first command configured to access the storage medium; and execute the first command using the data in the first buffer.

Abstract: A memory sub-system, including: a random access memory; a storage medium having a storage capacity accessible to a host system through commands communicated via a plurality of submission queues to the memory sub-system; and a controller. The controller is configured to: retrieve, from a first submission queue among the plurality of submission queues, a first command configured with a first address to access the storage medium; determine, based at least in part on the first command, that a second address configured in a second command following the first command in communication via the first submission queue from the host system to the memory sub-system is predictable; predict a third address according to the first address configured in the first command; and retrieve, from the storage medium and according to the third address, a data chunk into the random access memory, before the second command is retrieved.