Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller or processing device of a host system adds an entry to a local shared work queue of the host system. The entry includes an NVMe command to be executed by the SSD. The entry also includes an address for a shared work queue of the SSD. The controller or processing device writes the command to the shared work queue of the SSD using a PCIe memory write. The command is then executed by the SSD.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, a memory sub-system (e.g., SSD) includes: at least one non-volatile memory device (e.g., flash memory); and at least one controller configured to: provide access to at least one shared work queue by exposing a portion of memory to a host system (e.g., GPU); receive, in the shared work queue, a command from the host system (e.g., NVMe command over PCIe fabric); and in response to receiving the command, copy the command to an internal command queue (e.g., queue of the SSD) for execution to access the non-volatile memory device according to an operation (e.g., read/write) identified in the command.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host/processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host/processor can send a command to enable/disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., CPU). Each command specifies an address space identifier (e.g., PASID). In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. The address space identifier is used (e.g., by a DMA engine) when performing a data transfer as part of the operation.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes an NVMe command to the SSD using a PCIe transaction layer packet. The command is written using either a deferred memory write or a memory write according to the PCIe standard. The command is written to the SSD either directly or via a local shared work queue of the host system.

Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is reconfigured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., GPU). Each command specifies an address for a completion record. In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. Then, the controller writes the completion record to a location in main memory of the host system at the address.

Abstract: A host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. The request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. The request can be implemented via a store instruction, a write command, or another command having another command identifier.

Abstract: An input/output (I/O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to establish a network connection to a cryptocurrency network, receive a proof of space challenge, and generate a response to the challenge using a plot stored in the memory cells.

Abstract: Various embodiments provide for performing one or more data read-ahead operations on a memory system based on a read size and a queue identifier of a read request. In particular, a memory system of some embodiments is configured to perform at least one read-ahead operation when an individual read request, received from a host system in association with a queue identifier, has a read size equal to a maximum data transfer size (MDTS) of the memory system.

Abstract: A memory sub-system having: a random access memory; a storage medium accessible to a host system using commands communicated via a plurality of submission queues to the memory sub-system; and a circuit configured to allocate, from the random access memory, one or more buffers that are associated respectively with one or more submission queues among the plurality of submission queues. The memory sub-system can: load data from the storage medium of the memory sub-system to a first buffer among the one or more buffers; retrieve, from a first submission queue associated with the first buffer among the plurality of the submission queues, a first command configured to access the storage medium; and execute the first command using the data in the first buffer.

Abstract: A memory sub-system, including: a random access memory; a storage medium having a storage capacity accessible to a host system through commands communicated via a plurality of submission queues to the memory sub-system; and a controller. The controller is configured to: retrieve, from a first submission queue among the plurality of submission queues, a first command configured with a first address to access the storage medium; determine, based at least in part on the first command, that a second address configured in a second command following the first command in communication via the first submission queue from the host system to the memory sub-system is predictable; predict a third address according to the first address configured in the first command; and retrieve, from the storage medium and according to the third address, a data chunk into the random access memory, before the second command is retrieved.

Abstract: A method to facilitate communications between a memory sub-system and a host system, including: allocating, from a random access memory of the memory sub-system, a first buffer to buffer data to be used during execution of commands communicated to the memory sub-system via a first submission queue from the host system; retrieving, from the first submission queue, a command; determining a size of a data chunk used during execution of the command; determining a preferred size of the first buffer based on the size of the data chunk; determining whether to change the first buffer according to the preferred size; and changing the first buffer to the preferred size.

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.

Abstract: The disclosure configures a memory sub-system controller to perform Redundant Array of Independent Disks (RAID) stripe deletion based on physical region size. The controller stores a set of data across a plurality of memory components, a first of the plurality of components being configured to store data in a first set of regions, a second of the plurality of components being configured to store data in a second set of regions. The controller generates a plurality of error correction parity information stripes for multiple collections of the set of data and computes a quantity of the plurality of error correction parity information stripes to delete based on sizes of each region in the first and second sets of regions. The controller deletes one or more of the plurality of error correction parity information stripes based on the computed quantity.

Abstract: Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.

Abstract: A method to process submission queues configured in a random access memory to provide storage access commands from a host system to a memory sub-system. The host system provides, in association with a particular submission queue, an identification number of a command entered in the submission queue. Based on the identification number provided by the host system in association with the submission queue, the memory sub-system can determine a count of commands in the submission queue. Based on at least on the count for the submission queue (and similar counts for other submission queues), the memory sub-system can identify one or more submission queues among the plurality of submission queues and retrieve a subset of the storage access commands for execution.