Abstract: A memory sub-system having: first memory cells (e.g., DRAM) configured to provide a memory space accessible to a host system via a memory access protocol (e.g., compute express link (CXL) or component interconnect express (PCIe)); and second memory cells (e.g., flash memory) configured to provide a storage space accessible to the host system via a submission queue using a storage access protocol (e.g., non-volatile memory express (NVMe)). A controller in the memory sub-system is configured to: allocate to the host system a plurality of memory blocks from the memory space; and send to the host system, a request for freeing at least a portion of the memory blocks.

Abstract: A memory sub-system having: first memory cells of a first type (e.g., SRAM); second memory cells of a second type (e.g., DRAM); third memory cells of a third type (e.g., flash memory) configured to provide a storage space accessible via commands entered in a submission queue. A controller in the memory sub-system is configured to: implement, using at least a portion of the first memory cells, a first logical memory device over a compute express link fabric; implement, using at least a portion of the second memory cells, a second logical memory device over the compute express link fabric; retrieve, from the submission queue, a request; allocate a memory block during execution of the request, the memory block having an address in the first logical memory device or the second logical memory device; and provide the address in a completion record for the request.

Abstract: A host system connected to a memory sub-system via a connection to query memory attachment capabilities of the memory sub-system in providing memory services over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to the query, the memory sub-system can provide a response containing data indicative of memory attachment capabilities of the memory sub-system. The host system can configure the memory services of the memory sub-system, such as a solid-state drive, based on the data received as a response to the query. The query and response can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access.

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems that support and provide redundant coverage for multiple hosts are described. The grouped set of chained subsystems can provide dedicated storage locations for each of the multiple hosts during normal operations. When one of the hosts fail, the grouped set can reconfigure the internal accessing scheme, thereby allowing the surviving host to see and access locations and data that was initially assigned to the failed host.

Abstract: A memory sub-system, including: a random access memory; a storage medium having a storage capacity accessible to a host system through commands communicated via a plurality of submission queues to the memory sub-system; and a controller. The controller is configured to: retrieve, from a first submission queue among the plurality of submission queues, a first command configured with a first address to access the storage medium; determine, based at least in part on the first command, that a second address configured in a second command following the first command in communication via the first submission queue from the host system to the memory sub-system is predictable; predict a third address according to the first address configured in the first command; and retrieve, from the storage medium and according to the third address, a data chunk into the random access memory, before the second command is retrieved.

Abstract: The disclosure configures a memory sub-system controller to perform scalable write amplification (WAF) measurement. The controller receives a request to place a memory sub-system into a WAF mode and, in response, reduces a full capacity of the memory sub-system to a reduced capacity by restricting write operations to an individual portion of a set of memory components. The controller generates a log that tracks a number of write operations performed to store data to the individual portion of the set of memory components relative to a plurality of requests to program the data to the individual portion of the memory sub-system. The controller computes, based on the log, the WAF for the full capacity of the memory sub-system based on the WAF of the reduced capacity of the memory sub-system.

Abstract: A memory sub-system including: first memory cells (e.g., of a flash memory) configured to provide a storage space accessible to a host system via entering requests in a plurality of submission queues (e.g., according to a standard for NVMe); and second memory cells (e.g., of a random access memory) configured to provide a memory space accessible to the host system. A controller of the memory sub-system is configured to: identify a batch of first requests pending in the submission queues; determine a memory allocation scheme configured to identify, in the memory space, placements of memory blocks to be allocated for the first requests; and execute, after the memory allocation scheme is determined, the first requests.

Abstract: A memory sub-system having: memory cells of a first type to provide a first portion of a memory space; memory cells of a second type to provide a second portion of the memory space; and memory cells of a third type to provide a storage space. A controller of the memory sub-system is configured to: receive a request identifying at least one memory attribute specified by a host system; allocate, in view of the at least one memory attribute, a memory block from the memory space; and provide the host system with a response to the request to identify a memory address of the memory block.

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots stored outside of the SSD. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to receive and store configuration data specified via a user interface to indicate a location, outside of the SSD, storing a proof of space plot that can be used by the SSD to participate in proof of space activities in a cryptocurrency network.

Abstract: A memory sub-system having: a random access memory configured to provide a memory space accessible, using a memory access protocol, by a host system over a connection between the host system and the memory sub-system; a non-volatile memory configured to provide a physical storage space accessible, via a storage access protocol, by the host system. The memory sub-system can: allocate, from the random access memory, a memory block; map the memory block to a logical memory region in a logical memory space; and establish, via a predetermined mapping between the logical storage space and the logical memory space, mapping between a logical block address, configured in a logical storage space and usable to access a portion of the non-volatile memory using the storage access protocol, and the memory block.

Abstract: A memory sub-system having: random access memory cells configured to provide a memory space accessible, via a memory access protocol, by a host system located outside of the memory sub-system; and non-volatile memory cells configured to provide a physical storage space accessible, via a storage access protocol, by the host system. The memory sub-system can: allocate, from the memory space, a plurality of memory blocks of varying sizes; establish mapping between a plurality of logical memory regions of a same size in a logical memory space and the plurality of memory blocks respectively; buffer data, addressable by the host system via a logical block address in a logical storage space according to the storage access protocol, in a memory block among the plurality of memory blocks; and establish mapping between the memory block and the logical block address via the logical memory space.

Abstract: A memory sub-system having: memory cells of a first type to provide a memory space; and memory cells of a second type to provide a physical storage space. A controller of the memory sub-system is configured to: store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; store, the memory space, a copy of a data portion addressable in the logical storage space; configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; and store information to identify a location, in the memory space, at which the data portion is cached or buffered.

Abstract: A memory sub-system having a memory space accessible to a host system using a memory access protocol and a storage space accessible to the host system using a storage access protocol. The memory sub-system is configured to: execute a storage access request identifying a logical block address in the storage space; store information indicating resources used in execution of the storage access request; receive a notification indicating a completion of access made via at least the storage access request; and free the resources based on the information and in response to the notification. For example, the resources can include a block of memory allocated from the memory space and/or used during the execution of the storage access request.

Abstract: A memory sub-system having a memory space accessible to a host system using a memory access protocol, and a storage space accessible to the host system using a storage access protocol. The memory sub-system is configured to: execute a storage access request to retrieve, from at least a logical block address in the storage space, data according the logical block address provided in the storage access request; allocate, in response to the storage access request, a block of memory from the memory space; store at least a portion of the data in the block of memory; and provide, in a completion record for the storage access request, a starting memory address of the block of memory.

Abstract: A memory sub-system having first memory cells configured to provide a memory space, and second memory cells configured to provide a storage space. A controller of the memory sub-system is configured to: allocate, in response to a memory allocation request from a host system connected to the memory sub-system, a block of memory from the memory space; and communicate, to the host system, a starting memory address of the block of memory. The memory allocation request can be retrieved from a submission queue configured for the memory sub-system in accordance of a storage access protocol (e.g., non-volatile memory express (NVMe)); and the starting memory address can be provided in a completion record for the memory allocation request in a completion queue in accordance of the storage access protocol.

Abstract: A host system having a memory controller operable on a connection from the memory controller to a host interface of a memory sub-system, and a processing device configured to: provide a storage access request to the memory sub-system to read a data block from a storage space of the memory sub-system into a memory space of the memory sub-system; receive a completion record for the storage access request; and execute, responsive to the completion record indicating successful completion of execution of the storage access request in the memory sub-system, at least one load instruction to load, based on a memory map in the memory controller identifying the memory space of the memory sub-system, a selected portion of the data block from the memory sub-system over the connection without loading a remaining portion the data block over the connection.

Abstract: A memory sub-system having: a host interface operable on a connection from the host interface to a host system outside of the memory sub-system; random access memory cells configured to provide a memory space accessible to the host system over the connection via a memory access protocol; non-volatile memory cells configured to provide a storage space accessible to the host system over the connection via a storage access protocol; and a controller configured to execute a storage access request, received from the host system over the connection according to the storage access protocol, to read data into the memory space from a logical block address in the storage space. The controller can also execute a storage access request, received over the connection according to the storage access protocol, to write data available in the memory space to a logical block address in the storage space.

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

Abstract: A system having a processing device, a memory sub-system having a memory space accessible via a memory access protocol and a storage space accessible via a storage access protocol, and a computer bus connecting the memory sub-system and the host system. The processing device is to configure a storage access request to identify a logical block address in the storage space and a first memory address in the memory space in the memory sub-system. The memory sub-system is to identify, based on the first memory address during execution of the storage access request, a plurality of memory addresses consecutive in the memory space, and execute the storage access request to: read data from the logical block address to the plurality of memory addresses in the memory space; or write, to the logical block address, data at the plurality of memory addresses in the memory space.

Abstract: A memory sub-system having: a plurality of host interfaces operable to communicate concurrently over a plurality of connections respectively; memory cells configured to provide a memory space accessible to a host system via the connections and a storage space separate from the memory space and accessible to the host system via the connections; and a controller configured to communicate with the host system via a first connection, among the plurality of connections, to execute a first request to access the storage space and concurrently communicate with the host system via a second connection, among the plurality of connections, to respond to a second request to access the memory space.