Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight.

Abstract: A processing device in a memory system receives a request to read data stored on a first plane of a plurality of planes of a memory device while a plurality of write operations are ongoing, wherein each of the plurality of write operations are performed concurrently to write each of a plurality of single-plane segments of data to a corresponding plane of the plurality of planes of the memory device, and wherein a multi-plane segment of data received with a write request is divided into the plurality of single-plane segments of data. The processing device further suspends a first write operation of the plurality of write operations, the first write operation corresponding to the first plane, and performs a read operation to read the data stored on the first plane while continuing to perform at least one other write operation of the plurality of write operations corresponding to another plane of the plurality planes.

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During a burn-in operation of the memory sub-system in a manufacturing facility, the memory sub-system is configured to perform read/write operations for the generation of a proof of space plot. After the burn-in operation, the memory sub-system is provided as a product of the manufacturing facility; and the proof of space plot stored in the memory sub-system is provided as a by-product of the burn-in operation.

Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.

Abstract: An apparatus with a solid state drive (SSD) having an internal host to control proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The internal host operable is to generate, independent of the external host system, commands related to proof of space, such as plot generation, and plot farming.

Abstract: A memory sub-system to show proof of space and identity. The memory sub-system can have a processing device, a storage medium operable to store a proof of space plot, and an integrated circuit having a unique device secret. In response to a proof of space challenge, the processing device can generate a response to the challenge using data in the proof of space plot. The integrated circuit is configured to compute, based on the unique device secret and for a communication associated with the proof of space challenge, identity data representative of an identity of the proof of space plot stored in the memory sub-system. The memory sub-system can provide the identity data in the communication.

Abstract: An apparatus with a solid state drive (SSD) having firmware to perform peer to peer transfer of proof of space plots. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD according to configuration data to: identify an opportunity for a transfer of a proof of space plot; establish a peer to peer connection to a device that is separate from the solid state drive; and transfer, over the peer to peer connection, the proof of space plot between the solid state drive and the device.

Abstract: An apparatus with a solid state drive (SSD) having firmware to manage spare storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to allocate storage resources not used or allocated by the host system to support proof of space activities and dynamically return the allocated storage resources when execution of a command from the host system needs additional storage resources.

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to establish a network connection to a cryptocurrency network, receive a proof of space challenge, and generate a response to the challenge using a plot stored in the memory cells.

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The SSD has a computation accelerator adapted to accelerate computations involved in generation of proof of space plots, such as computations of Basic Linear Algebra Subprograms (BLAS), multiplication and accumulation operations, and cryptographic operations.

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.

Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: determining, by a host system, that a failure affects a storage capacity of a memory sub-system, wherein the memory sub-system comprises stored data of a storage structure; instructing, by the host system, the memory sub-system to operate at a reduced capacity and to retain the stored data of the storage structure; receiving, by the host system, a set of storage units of the memory sub-system that are affected by the failure; and recovering, by the host system, data that was in the set of storage units affected by the failure.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

Abstract: A memory device comprises a file system and a processing device to perform operations comprising receiving, from the file system, a first data access command comprising a payload, responsive to receiving the first data access command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the first data access command is for data or for metadata, and sending a second data access command to a memory sub-system, wherein the second data access command includes an indication of a memory region of a memory device in which the memory sub-system is to store the payload, wherein the indication of the memory region is based on the characteristic of the payload.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.