Patents by Inventor Luca Bert

Luca Bert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240220132
    Abstract: A memory sub-system, such as a solid-state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Patent number: 12015706
    Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Publication number: 20240193085
    Abstract: A memory sub-system having a paging system to provide memory services over a connection from its host interface to a host system. The connection can support both a storage access protocol and a cache coherent memory access protocol. The memory sub-system can have a non-volatile memory to provide a storage capacity and a fast, volatile memory to cache active pages of a memory space provided by a memory device attached by the memory sub-system over the connection to the host system. The memory space can be configured in a namespace of the storage capacity of the non-volatile memory. Optionally, the memory space can be configured for access both via the storage access protocol using logical block addresses and via the cache coherent memory access protocol using memory addresses.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 13, 2024
    Inventor: Luca Bert
  • Publication number: 20240192883
    Abstract: An apparatus with a solid state drive (SSD) having firmware to manage spare storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to allocate storage resources not used or allocated by the host system to support proof of space activities and dynamically return the allocated storage resources when execution of a command from the host system needs additional storage resources.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Publication number: 20240184783
    Abstract: Host system failover via a memory sub-system storing in-memory data for database operations. Over a connection from a host interface of the memory sub-system, a first portion of the memory sub-system can be attached to a first host system as a memory device accessible via a first protocol; and a second portion of the memory sub-system can be attached to the first host system as a storage device accessible via a second protocol. A database manager running in the first host system can store the in-memory data in the memory device and store a persistent copy of database records in the storage device. When the first host system fails, the memory sub-system can be reconnected to a second host system to use the in-memory data for continued database operations.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 6, 2024
    Inventor: Luca Bert
  • Publication number: 20240184694
    Abstract: A computing device having a computer express link (CXL) connection between a memory sub-system and a host system to write records of a database into a storage portion of the memory sub-system and store data identifying changes to the database into a memory portion of the memory sub-system. The records can be written to the storage portion using a storage access protocol of the CXL connection; and the change data can be stored to the memory portion using a cache coherent memory access protocol of the CXL connection. The change data can be written from the memory portion to a file in the storage portion.
    Type: Application
    Filed: November 13, 2023
    Publication date: June 6, 2024
    Inventor: Luca Bert
  • Publication number: 20240176735
    Abstract: A host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. The request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. The request can be implemented via a store instruction, a write command, or another command having another command identifier.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 30, 2024
    Inventor: Luca Bert
  • Publication number: 20240176535
    Abstract: A method to provide network storage services to a remote host system, including: generating, from packets received from the remote host system, first control messages and first data messages; buffering, in a random-access memory of a memory sub-system, the first control messages for a local host system to fetch the first control messages, process the first control messages, and generate second control messages; sending the first data messages to a storage device of the memory sub-system without the first data messages being buffered in the random-access memory; communicating the second control messages generated by the local host system to the storage device of the memory sub-system; and processing, within the storage device, the second control messages and the first data messages to provide the network storage services.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventor: Luca Bert
  • Publication number: 20240176745
    Abstract: A host system connected to a memory sub-system via a connection to query memory attachment capabilities of the memory sub-system in providing memory services over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to the query, the memory sub-system can provide a response containing data indicative of memory attachment capabilities of the memory sub-system. The host system can configure the memory services of the memory sub-system, such as a solid-state drive, based on the data received as a response to the query. The query and response can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 30, 2024
    Inventor: Luca Bert
  • Patent number: 11983434
    Abstract: A storage product manufactured as a component to be installed in a computing device to provide network storage services. The storage product has a network interface to receive storage access messages from a remote host system, a bus connector connectable via an external computer bus to an external local host system, a local storage device, and a computational storage processor. The storage product is configured to: separate the storage access messages into first messages, second messages, and third messages; provide the first messages to an external local host system to generate fourth messages; and provide the second messages to the computational storage processor to generate fifth messages. To implement network storage services provided via the network interface, the local storage device executes commands in the third messages, the fourth messages from the local host system, and the fifth messages from the computational storage processor.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11983107
    Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11977742
    Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots stored outside of the SSD. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to receive and store configuration data specified via a user interface to indicate a location, outside of the SSD, storing a proof of space plot that can be used by the SSD to participate in proof of space activities in a cryptocurrency network.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Publication number: 20240143422
    Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.
    Type: Application
    Filed: December 21, 2023
    Publication date: May 2, 2024
    Inventor: Luca Bert
  • Patent number: 11966638
    Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically generate Redundant Array of Independent Nodes (RAIN) parity information for zone-based memory allocations. The RAIN parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. The zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11960756
    Abstract: An apparatus with a solid state drive (SSD) having firmware to manage spare storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to allocate storage resources not used or allocated by the host system to support proof of space activities and dynamically return the allocated storage resources when execution of a command from the host system needs additional storage resources.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Publication number: 20240118950
    Abstract: A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventor: Luca Bert
  • Patent number: 11947834
    Abstract: A method to provide network storage services to a remote host system, including: generating, from packets received from the remote host system, first control messages and first data messages; buffering, in a random-access memory of a memory sub-system, the first control messages for a local host system to fetch the first control messages, process the first control messages, and generate second control messages; sending the first data messages to a storage device of the memory sub-system without the first data messages being buffered in the random-access memory; communicating the second control messages generated by the local host system to the storage device of the memory sub-system; and processing, within the storage device, the second control messages and the first data messages to provide the network storage services.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11941254
    Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Publication number: 20240069739
    Abstract: An input/output (I/O) write request directed at memory devices is received by a processing device. The write request includes a data object. The memory devices include groups of memory cells corresponding to sequential logical addresses. The data object is appended to a compound data object associated with one of the memory devices. The compound data object is associated with the groups of memory cells. A first group of memory cells is in the not-full state, and one or more subsequent, in an order corresponding to the sequential logical addresses, groups of memory cells is identified as a free group of memory cells. The compound data object is caused to be written to the groups of memory cells, resulting in the full state of the first group of memory cells and resulting in the not-full state of at least one of the one or more subsequent groups of memory.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventor: Luca Bert
  • Publication number: 20240069992
    Abstract: A storage product manufactured as a standalone computer component, having a bus connector to an external processor, a storage device, a random-access memory, a computational storage processor, and a processing device to identify, among storage access messages from a computer network, first messages, second messages, and third messages. The random-access memory hosts first queues shared between the processing device and the external processor, and second queues shared between the processing device and the computational storage processor. The processing device can place the first messages in the first queues for the external processor to generate fourth messages, place the second messages in the second queues for the computational storage processor to generate fifth messages, and provide the third messages to the storage device. The storage device can process the third messages, the fourth messages, and the fifth messages to implement requests in the storage access messages.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventor: Luca Bert