Patents by Inventor Luca Bert

Luca Bert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250004655
    Abstract: A set of host data items is received for storage at a memory sub-system. Each of the set of host data items is associated with a common data type. A zone group size metric associated with the common data type is identified among a set of zone group size metrics each associated with a distinct data type. The set of host data items are programmed to memory cells of a zone group having a zone group size indicated by the zone group size metric.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Inventor: Luca Bert
  • Publication number: 20240419345
    Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. Subsequently, the SSD can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 12153798
    Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: November 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20240377964
    Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems that support and provide redundant coverage for multiple hosts are described. The grouped set of chained subsystems can provide dedicated storage locations for each of the multiple hosts during normal operations. When one of the hosts fail, the grouped set can reconfigure the internal accessing scheme, thereby allowing the surviving host to see and access locations and data that was initially assigned to the failed host.
    Type: Application
    Filed: April 19, 2024
    Publication date: November 14, 2024
    Inventors: Jonathan R. Hinkle, Luca Bert
  • Publication number: 20240378145
    Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.
    Type: Application
    Filed: April 19, 2024
    Publication date: November 14, 2024
    Inventors: Jonathan R. Hinkle, Luca Bert
  • Publication number: 20240378111
    Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.
    Type: Application
    Filed: April 19, 2024
    Publication date: November 14, 2024
    Inventors: Jonathan R. Hinkle, Luca Bert
  • Publication number: 20240378098
    Abstract: A standalone storage product having: a first bus connector for connecting to an external processor; a second bus connector for connecting to an external network interface; a storage device accessible over the network interface; and a processing device configured to communicate, via the second bus connector, with the network interface to obtain storage access messages represented by incoming packets received at the network interface from a computer network. The processing device can: identify, from the storage access messages, first messages and second messages; provide, the first messages via the first bus connector, to the processor; and provide, the second messages, to the storage device without the second messages going through the processor. The storage device is configured to: receive, via the first bus connector, third messages from the processor; and execute commands in the second messages and the third messages to implement a network storage service.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventor: Luca Bert
  • Patent number: 12141442
    Abstract: An input/output (I/O) write request directed at memory devices is received by a processing device. The write request includes a data object. The memory devices include groups of memory cells corresponding to sequential logical addresses. The data object is appended to a compound data object associated with one of the memory devices. The compound data object is associated with the groups of memory cells. A first group of memory cells is in the not-full state, and one or more subsequent, in an order corresponding to the sequential logical addresses, groups of memory cells is identified as a free group of memory cells. The compound data object is caused to be written to the groups of memory cells, resulting in the full state of the first group of memory cells and resulting in the not-full state of at least one of the one or more subsequent groups of memory.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: November 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20240370207
    Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During a burn-in operation of the memory sub-system in a manufacturing facility, the memory sub-system is configured to perform read/write operations for the generation of a proof of space plot. After the burn-in operation, the memory sub-system is provided as a product of the manufacturing facility; and the proof of space plot stored in the memory sub-system is provided as a by-product of the burn-in operation.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Patent number: 12131041
    Abstract: A system includes one or more memory devices and a processing device coupled to the memory device(s) to perform operations including receiving a first set of data items from a host system to be programmed to the one or more memory devices. The operations include determining, in view of a first zone group identifier associated with the first set of data items, that each data item of the first set of data items is to be programed to one or more zones associated with a first zone group identified by the first zone group identifier. The operations include identifying a first set of zones across the one or more memory devices that match a size associated with the first zone group and that satisfy a programming parallelism criterion. The operations include programming each of the first set of data items to memory cells residing at the identified first set of zones.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20240353999
    Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A source cursor associated with the victim MU is identified from an ordered set of cursors. A target cursor following the source cursor in the ordered set of cursors referencing one or more available MUs is identified. In response to determining that the source cursor is a last cursor in the ordered set of cursors, the source cursor is utilized as the target cursor. The valid data is associated with the identified target cursor.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventor: Luca Bert
  • Patent number: 12118220
    Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Patent number: 12111761
    Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20240333496
    Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 12105970
    Abstract: One or more requests are received by a processing device managing one or more memory devices of a memory sub-system from a host system to store a set of data items. A zone group corresponding to a size of the set of data items is identified. A set of zones of the zone group which satisfies a programming parallelism criterion is identified among two or more zones defined in the memory sub-system. The set of data items are programmed to memory cells of the identified set of zones.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 1, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20240320029
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device, the processing device is to create a namespace by allocating a reclaim group, the reclaim group comprising a plurality of reclaim units; assign a reclaim unit handle to the namespace; receive, from a virtual machine running on a host computing system, a command to perform an operation associated with the namespace; identify a segment of the memory device based on the reclaim unit handle that is assigned to the namespace; and perform the operation on the segment of the memory device.
    Type: Application
    Filed: February 28, 2024
    Publication date: September 26, 2024
    Inventor: Luca Bert
  • Patent number: 12086432
    Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. Subsequently, the SSD can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 12086468
    Abstract: A host command is received designating a first interface standard at a first port for exposing a storage element implemented by a non-volatile memory device and a second interface standard at a second port for exposing a persistent memory region (PMR) implemented as a power protected region of a volatile memory device. The non-volatile memory device and the volatile memory device are associated with a first switch for implementing the first interface standard and a second switch for implementing the second interface standard. The first interface standard supports one or more alternate protocols implemented by the second interface standard. The storage element is exposed by designating the first interface standard at the first port and the PMR by designating the second interface standard at the second port. A segment of the PMR is allocated as a cacheable memory marked as visible through, and shared through, the second interface standard.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph H. Steinmetz
  • Publication number: 20240295983
    Abstract: A storage product manufactured as a component to be installed in a computing device to provide network storage services. The storage product has a network interface to receive storage access messages from a remote host system, a bus connector connectable via an external computer bus to an external local host system, a local storage device, and a computational storage processor. The storage product is configured to: separate the storage access messages into first messages, second messages, and third messages; provide the first messages to an external local host system to generate fourth messages; and provide the second messages to the computational storage processor to generate fifth messages. To implement network storage services provided via the network interface, the local storage device executes commands in the third messages, the fourth messages from the local host system, and the fifth messages from the computational storage processor.
    Type: Application
    Filed: April 25, 2024
    Publication date: September 5, 2024
    Inventor: Luca Bert
  • Publication number: 20240289271
    Abstract: Memory sub-systems configured to manage storage locations of files for a host system. For example, a connection from a memory sub-system to the host system can support both a cache-coherent memory access protocol to a memory device implemented in the storage capacity of the memory sub-system and a storage access protocol. The memory sub-system can maintain, and share with the host system via the memory device, a medium map configured to identify, for a file stored in the memory sub-system, memory addresses usable for the host system to access locations in the file over the connection using the cache-coherent memory access protocol, and/or logical block addresses usable for the host system to access blocks of the files over the connection using the storage access protocol.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 29, 2024
    Inventor: Luca Bert