Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

Abstract: A host command is received to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternate protocols supported by the first interface standard. The system is configured in accordance with the configuration.

Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

Abstract: A system includes a plurality of nodes, a first memory device including a plurality of volumes each visible to at least one of the plurality of nodes within a visibility configuration, and a processing device, operatively coupled with the plurality of nodes and the first memory device. The processing device performs operations including identifying a system failure affecting visibility of at least one of the plurality of volumes of the first memory device, and modifying the visibility configuration to address the system failure.

Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.

Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: configuring the memory device with a zoned namespace comprising a plurality of zones; notifying a host system of a failure associated with a zone of the plurality of zones, wherein the failure affects stored data; receiving from the host system an indication to continue at a capacity that is reduced; recovering the stored data of the zone affected by the failure; and updating the set of memory devices to change the capacity to a reduced capacity.

Abstract: A request to write a first data item associated with a first thread to a memory device is received. The memory device includes a first portion and a second portion. The first portion includes a cache that includes a first block to be utilized for data caching and a second block and a third block to be used for block compaction. The second block is associated with a high modification frequency and the third block is associated with a low modification frequency. In response to determining a first memory page in the first block is available for writing the first data item, the first data item is written to the first memory page. A determination is made that a memory page criterion associated with the first thread has been satisfied.

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.

Abstract: A processing device in a memory system receives a request to execute a first operation of a first input/output (I/O) operation type at a memory device. The processing device further determines whether a second operation of a second I/O operation type is being executed at the memory device. Responsive to determining that the second operation is being executed, the processing device suspends the second operation after a delay time period, the delay time period corresponds to a first operation weight of the first operation and a second operation weight of the second operation, executes the first operation at the memory device, and responsive to determining that executing the first operation is complete, the processing device resumes execution of the second operation at the memory device.

Abstract: A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.

Abstract: A request to write a first data item associated with a first thread to a memory device is received. The memory device includes a first portion and a second portion. The first portion includes a cache that includes a first block to be utilized for data caching and a second block and a third block to be used for block compaction. The second block is associated with a high modification frequency and the third block is associated with a low modification frequency. In response to determining a first memory page in the first block is available for writing the first data item, the first data item is written to the first memory page. A determination is made that a memory page criterion associated with the first thread has been satisfied.

Abstract: A processing device in a memory system receives requests to perform a plurality of memory access operations at a memory device configured with a zone namespace having a plurality of zones, the memory device comprising a plurality of planes, wherein each zone of the plurality of zones is associated with a respective plane of the plurality of planes. The processing device further concurrently performs the plurality of memory access operations on data stored in different zones of the plurality of zones, wherein the different zones are associated with different planes of the plurality of planes.

Abstract: A processing device in a memory system receives a request to read data stored on a first plane of a plurality of planes of a memory device while a plurality of write operations are ongoing, wherein each of the plurality of write operations are performed concurrently to write each of a plurality of single-plane segments of data to a corresponding plane of the plurality of planes of the memory device, and wherein a multi-plane segment of data received with a write request is divided into the plurality of single-plane segments of data. The processing device further suspends a first write operation of the plurality of write operations, the first write operation corresponding to the first plane, and performs a read operation to read the data stored on the first plane while continuing to perform at least one other write operation of the plurality of write operations corresponding to another plane of the plurality planes.

Abstract: A processing device in a memory system receives a request to write a multi-plane segment of data to a memory device, the memory device comprising a plurality of planes. The processing device divides the multi-plane segment of data into a plurality of single-plane segments of data and concurrently performs a plurality of write operations to write each of the plurality of single-plane segments of data to a corresponding plane of the plurality of planes of the memory device.

Abstract: A processing device in a memory system receives requests to perform a plurality of memory access operations at a memory device configured with a zone namespace having a plurality of zones. The memory device includes a plurality of planes, wherein each zone of the plurality of zones is associated with a separate plane of the plurality of planes. The processing device further concurrently performs a first memory access operation of the plurality of memory access operations on first data stored in a first zone of the plurality of zones and a second memory access operation of the plurality of memory access operations on second data stored in a second zone of the plurality of zones, wherein the first zone is associated with a first plane of the plurality of planes, and wherein the second zone is associated with a second plane of the plurality of planes.

Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.