Patents by Inventor Luigi Colombo
Luigi Colombo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11938715Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.Type: GrantFiled: December 21, 2018Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Luigi Colombo, Nazila Dadvand, Benjamin Stassen Cook, Archana Venugopal
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Patent number: 11866848Abstract: A method of growing a cadmium zinc telluride (CdZnTe) crystal includes providing a crucible including a solid CdZnTe source and forming a Te-rich Cd—Zn—Te melt on the solid CdZnTe source. The method also includes positioning a CdZnTe seed crystal in physical contact with the Te-rich Cd—Zn—Te melt and growing the CdZnTe crystal from the Te-rich Cd—Zn—Te melt.Type: GrantFiled: June 18, 2020Date of Patent: January 9, 2024Inventors: Lance Robertson, Luigi Colombo, Victor Perez-Rubio, Tim Svoboda, Fred Raymel Harris, Kathryn O'Brien
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Publication number: 20230307312Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.Type: ApplicationFiled: May 4, 2023Publication date: September 28, 2023Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
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Publication number: 20230243770Abstract: A gas sensor has a microstructure sensing element which comprises a plurality of interconnected units wherein the units are formed of connected graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.Type: ApplicationFiled: March 8, 2023Publication date: August 3, 2023Applicant: Texas Instruments IncorporatedInventors: Archana VENUGOPAL, Benjamin Stassen Cook, Nazila Dadvand, Luigi Colombo
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Patent number: 11710764Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.Type: GrantFiled: June 27, 2018Date of Patent: July 25, 2023Assignee: Texas Instruments IncorporatedInventors: Poornika Fernandes, Sagnik Dey, Luigi Colombo, Haowen Bu, Scott Robert Summerfelt, Mark Robert Visokay, John Paul Campbell
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Patent number: 11676880Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.Type: GrantFiled: November 26, 2016Date of Patent: June 13, 2023Assignee: Texas Instruments IncorporatedInventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
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Patent number: 11670671Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.Type: GrantFiled: February 22, 2021Date of Patent: June 6, 2023Assignee: Texas Instruments IncorporatedInventors: Poornika Fernandes, Luigi Colombo, Haowen Bu
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Patent number: 11569342Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.Type: GrantFiled: March 16, 2020Date of Patent: January 31, 2023Assignee: Texas Instruments IncorporatedInventors: Poornika Fernandes, Luigi Colombo, Haowen Bu
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Publication number: 20220250909Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Inventors: Luigi COLOMBO, Nazila DADVAND, Benjamin Stassen COOK, Archana VENUGOPAL
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Patent number: 11390527Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice. A ceramic may be deposited on the graphene and another graphene layer may be deposited on top of the ceramic to create a multi-layered sp2-bonded carbon tube.Type: GrantFiled: December 21, 2018Date of Patent: July 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Nazila Dadvand, Luigi Colombo, Archana Venugopal
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Patent number: 11370662Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.Type: GrantFiled: December 21, 2018Date of Patent: June 28, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Luigi Colombo, Nazila Dadvand, Benjamin Stassen Cook, Archana Venugopal
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Publication number: 20220169773Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventors: Nazila DADVAND, Benjamin Stassen COOK, Archana VENUGOPAL, Luigi COLOMBO
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Patent number: 11309388Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.Type: GrantFiled: August 17, 2020Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Luigi Colombo, Nazila Dadvand, Archana Venugopal
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Patent number: 11296237Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.Type: GrantFiled: May 28, 2019Date of Patent: April 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Archana Venugopal, Luigi Colombo, Arup Polley
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Patent number: 11254775Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.Type: GrantFiled: December 21, 2018Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nazila Dadvand, Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo
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Patent number: 11145598Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.Type: GrantFiled: December 28, 2018Date of Patent: October 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Nazila Dadvand, Archana Venugopal, Luigi Colombo
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Publication number: 20210272804Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.Type: ApplicationFiled: May 10, 2021Publication date: September 2, 2021Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
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Patent number: 11081593Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.Type: GrantFiled: October 23, 2019Date of Patent: August 3, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Archana Venugopal, Luigi Colombo
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Patent number: 11063120Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.Type: GrantFiled: December 26, 2018Date of Patent: July 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Luigi Colombo, Archana Venugopal, Benjamin Stassen Cook, Nazila Dadvand
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Publication number: 20210202688Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.Type: ApplicationFiled: February 22, 2021Publication date: July 1, 2021Inventors: Poornika Fernandes, Luigi Colombo, Haowen Bu