Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice. A ceramic may be deposited on the graphene and another graphene layer may be deposited on top of the ceramic to create a multi-layered sp2-bonded carbon tube.

Abstract: In described examples, a 3D magnetic sensing block includes a plurality of interconnected unit cells including at least a first unit cell formed of first interconnected conducting segments, and a second unit cell formed of second interconnected conducting segments. The plurality of interconnected unit cells forms a lattice. The first unit cell is a first sensing element, and the second unit cell is a second sensing element.

Abstract: A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.

Abstract: A structure includes a metal layer and a graphene sheet having at least one hole. The graphene sheet is contained at least partly within the metal layer.

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

Abstract: A gas sensor has a microstructure sensing element which comprises a plurality of interconnected units wherein the units are formed of connected graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function<4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.