Abstract: Fabricating a crystalline metal-phosphide layer may include providing a crystalline base substrate and a step of forming a crystalline metal-source layer. The method may further include performing a chemical conversion reaction to convert the metal-source layer to the crystalline metal phosphide layer. One or more corresponding semiconductor structures can be also provided.

Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.

Abstract: An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

Abstract: Embodiments of the invention are directed to a method of fabrication of an electro-optical device. A non-limiting example of the method relies on a waveguide. A trench is opened in the waveguide and a stack of optically active semiconductor materials is directly grown from a bottom wall of the trench and are stacked along a stacking direction that is perpendicular to a main plane of the waveguide. The stack is partly encapsulated in the waveguide, whereby a bottom layer of the stack is in direct contact with a waveguide core material, whereas upper portions of opposite, lateral sides of the stack are exposed. An insulating layer of material is deposited to cover exposed surfaces of the waveguide and structured to form a lateral growth template. Contact layers are laterally grown due to the lateral growth template formed. The contact layers can include an n-doped and p-doped contact layers.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: Embodiments are directed to the fabrication of an electro-optical device. The device comprises the forming of an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises selectively re-growing two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.

Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.

Abstract: Embodiments of the invention are directed to a method of fabrication of an electro-optical device. A non-limiting example of the method relies on a waveguide. A trench is opened in the waveguide and a stack of optically active semiconductor materials is directly grown from a bottom wall of the trench and are stacked along a stacking direction that is perpendicular to a main plane of the waveguide. The stack is partly encapsulated in the waveguide, whereby a bottom layer of the stack is in direct contact with a waveguide core material, whereas upper portions of opposite, lateral sides of the stack are exposed. An insulating layer of material is deposited to cover exposed surfaces of the waveguide and structured to form a lateral growth template. Contact layers are laterally grown due to the lateral growth template formed. The contact layers can include an n-doped and p-doped contact layers.

Abstract: A silicon photonic chip includes a silicon on insulator wafer and an electro-optical device on the silicon on insulator wafer. The electro-optical device is a lateral current injection electro-optical device that includes a slab having a pair of structured doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair of structured doped layers includes an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer is configured as a two-dimensional photonic crystal. A separation section extends between the pair of structured doped layers, the separation section fully separates the p-doped layer from the n-doped layer. The separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Abstract: An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

Abstract: Fabricating a crystalline metal-phosphide layer may include providing a crystalline base substrate and a step of forming a crystalline metal-source layer. The method may further include performing a chemical conversion reaction to convert the metal-source layer to the crystalline metal phosphide layer. One or more corresponding semiconductor structures can be also provided.

Abstract: A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

Abstract: An ultra-thin-body GaN-on-Insulator device and a method of manufacturing may be provided. The device comprises a front-end-of-line processed CMOS platform terminated with an interlayer dielectric material, a first bonding layer atop the interlayer dielectric material and an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer. The GaN-based hetero-structure is bonded with the second bonding layer to the first bonding layer of the CMOS platform building the ultra-thin-body GaN-on-Insulator device.

Abstract: A quantum processing apparatus comprises control electronics, a switching unit, a bias line, and N electronic circuits. Both the switching unit and the bias line are connected to the control electronics. The N circuits comprise N respective, non-volatilely tunable resistors and N respective frequency-tunable, solid-state qubits. The control electronics are configured to individually tune the resistors via the switching unit, in a configuration mode of the apparatus; and apply a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus. The electronic circuits are configured to passively apply respective bias signals to the qubits, wherein such bias signals are impacted by the resistors, in response to the voltage bias applied via the bias line, to operate the qubits at respective frequencies determined according to the respective bias signals.

Abstract: A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.