Patents by Inventor Lukas Czornomaz
Lukas Czornomaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180006069Abstract: A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid
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Publication number: 20170364623Abstract: Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.Type: ApplicationFiled: June 15, 2016Publication date: December 21, 2017Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170345654Abstract: A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Inventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Publication number: 20170345656Abstract: A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.Type: ApplicationFiled: July 15, 2017Publication date: November 30, 2017Inventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Patent number: 9823414Abstract: A semiconductor device for use in an optical application and a method for fabricating the device. The device includes: an optically passive aspect that is operable in a substantially optically passive mode; and an optically active material having a material that is operable in a substantially optically active mode, wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure, and the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect.Type: GrantFiled: June 10, 2016Date of Patent: November 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Jens Hofrichter, Mirja Richter, Heike E. Riel
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Publication number: 20170294307Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.Type: ApplicationFiled: June 20, 2017Publication date: October 12, 2017Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9786664Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: GrantFiled: February 10, 2016Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9748098Abstract: After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.Type: GrantFiled: August 15, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
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Patent number: 9735010Abstract: A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.Type: GrantFiled: May 27, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Publication number: 20170229460Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1?x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: February 10, 2016Publication date: August 10, 2017Inventors: Lukas CZORNOMAZ, Veeresh Vidyadhar DESHPANDE, Vladimir DJARA, Jean FOMPEYRINE
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Publication number: 20170229352Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: April 10, 2017Publication date: August 10, 2017Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9704757Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.Type: GrantFiled: February 25, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170194145Abstract: After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.Type: ApplicationFiled: August 15, 2016Publication date: July 6, 2017Inventors: Karthik Balakrishnan, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
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Patent number: 9673104Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.Type: GrantFiled: February 10, 2016Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9640394Abstract: Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.Type: GrantFiled: August 26, 2015Date of Patent: May 2, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Publication number: 20170117187Abstract: A method, and the resulting structure, of a semiconductor device where a first and second gate structure is formed above a Semiconductor-on-Insulator (SOI) material. Following any detrimental processes used to form the first gate structure, the base semiconductor material is exposed and the semiconductor material beneath the second gate structure is removed. A new semiconductor material is grown from the exposed base semiconductor material, and through the second gate structure, creating a device having FET and FinFET devices containing 2 different semiconductor materials.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventors: Takashi Ando, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
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Publication number: 20170097468Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Lukas Czornomaz, Jean Fompeyrine, Jens Hofrichter, Bert Jan Offrein, Mirja Richter
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Patent number: 9570169Abstract: A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for storing information in a plurality of resistance states, a second segment including a non-insulating material, a first terminal, a second terminal, and a third terminal. The first segment and the second segment are arranged in parallel between the first terminal and the second terminal. The control unit is configured to apply in a write mode a write voltage to the first and the second terminal for writing the resistance state, and to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state, and to apply a control signal to the third terminal for adjusting the electrical resistance of the second segment. A related method and control unit are also disclosed.Type: GrantFiled: June 3, 2016Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
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Patent number: 9564452Abstract: A method is disclosed for fabricating a semiconductor circuit. A semiconductor substrate is provided. A first semiconductor device is fabricated including a first semiconductor material on the substrate and forming an insulating layer including a cavity structure on the first semiconductor device. The cavity structure includes at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure including a second semiconductor material different from the first semiconductor material in the growth channel, forming a semiconductor starting structure for a second semiconductor device from the filling structure, and fabricating a second semiconductor device including the starting structure. Corresponding semiconductor circuits are also disclosed.Type: GrantFiled: February 1, 2016Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170011913Abstract: Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli