Abstract: A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: The present invention is notably directed to an electro-optical device. This device has a layer structure, which comprises a stack of III-V semiconductor gain materials, an n-doped layer and a p-doped layer. The III-V materials are stacked along a stacking direction z, which is perpendicular to a main plane of the stack. The n-doped layer extends essentially parallel to the main plane of the stack, on one side thereof. The p-doped layer too extends essentially parallel to this main plane, but on another side thereof. A median vertical plane can be defined in the layer structure, which plane is parallel to the stacking direction z and perpendicular to the main plane of the stack. Now, the device further comprises two sets of ohmic contacts, wherein the ohmic contacts of each set are configured for vertical current injection in the stack of III-V semiconductor gain materials.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Abstract: Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Abstract: A radiation detector and method and computer program product for detecting radiation. The detector comprises a waveguide structure, a sensing structure comprising a phase change material, an optical transmitter and optical receiver. The optical transmitter transmits an optical sensing signal for receipt at the optical receiver via the waveguide structure. The phase change material comprises a first phase state at a first temperature range and a second phase state at a second temperature range and transitions from the first phase state to the second phase state under exposure of the radiation. The sensing structure is arranged in an evanescent field area of the waveguide structure and provides for an evanescent field of the optical sensing signal a first complex refractive index in the first phase state and a second complex refractive index in the second phase state. The first complex refractive index is different from the second complex refractive index.

Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

Abstract: A method, and the resulting structure, of a semiconductor device where a first and second gate structure is formed above a Semiconductor-on-Insulator (SOI) material. Following any detrimental processes used to form the first gate structure, the base semiconductor material is exposed and the semiconductor material beneath the second gate structure is removed. A new semiconductor material is grown from the exposed base semiconductor material, and through the second gate structure, creating a device having FET and FinFET devices containing 2 different semiconductor materials.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.