Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.

Abstract: A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Abstract: A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Abstract: A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

Abstract: A silicon photonic chip includes a silicon on insulator wafer and an electro-optical device on the silicon on insulator wafer. The electro-optical device is a lateral current injection electro-optical device that includes a slab having a pair of structured doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair of structured doped layers includes an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer is configured as a two-dimensional photonic crystal. A separation section extends between the pair of structured doped layers, the separation section fully separates the p-doped layer from the n-doped layer. The separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Abstract: A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Abstract: A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Abstract: The present invention is notably directed to an electro-optical device. This device has a layer structure, which comprises a stack of III-V semiconductor gain materials, an n-doped layer and a p-doped layer. The III-V materials are stacked along a stacking direction z, which is perpendicular to a main plane of the stack. The n-doped layer extends essentially parallel to the main plane of the stack, on one side thereof. The p-doped layer too extends essentially parallel to this main plane, but on another side thereof. A median vertical plane can be defined in the layer structure, which plane is parallel to the stacking direction z and perpendicular to the main plane of the stack. Now, the device further comprises two sets of ohmic contacts, wherein the ohmic contacts of each set are configured for vertical current injection in the stack of III-V semiconductor gain materials.

Abstract: A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.

Abstract: Embodiments of the disclosure are directed to the fabrication of an electro-optical device. The device comprises the forming of an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises selectively re-growing two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices.

Abstract: A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.

Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.

Abstract: A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Abstract: An ultra-thin-body GaN-on-Insulator device and a method of manufacturing may be provided. The device comprises a front-end-of-line processed CMOS platform terminated with an interlayer dielectric material, a first bonding layer atop the interlayer dielectric material and an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer. The GaN-based hetero-structure is bonded with the second bonding layer to the first bonding layer of the CMOS platform building the ultra-thin-body GaN-on-Insulator device.