Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one clock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

Abstract: The invention relates to a phase detector. The phase detector includes data sampling cells to sample a stream of serial data and generate primary data samples and also includes edge data sampling cells to sample the stream of serial data and generate edge data samples. The phase detector further includes phase detecting cells to generate phase control signals. Each phase detecting cell includes a first circuit to receive data and sampled edge data and to generate a first signal and a second signal. The first signal from a phase detecting cell is a delayed sampled edge data. The second signal from that phase detecting cell will be a delayed sampled edge data before data is sampled by the data sampling cell. Once data is sampled by the data sampling cell, the second signal from that phase detecting cell will be a secondary data sample. Each phase detecting cell also includes a comparator circuit to receive the first signal and second signal and to generate a phase control signal therefrom.

Abstract: A number of control signals are provided, where each is responsive to a phase error measured at a different time between a first oscillatory signal and a number of second oscillatory signals. A node is either charged or discharged using a number of charged storage devices, where each device has a predetermined capacitance, in response to the number of first control signals. The method is applicable in frequency control circuit applications such as phase locked loops (PLLs), delay locked loops (DLLs) and clock recovery circuits (CRCs).

Abstract: The present invention is directed to receiver impedance calibration arrangements in full duplex communication systems.

Abstract: A method and apparatus for high-speed serial data recovery. The apparatus comprises providing a storage device to store data and a block to adjust the position of the data in the storage device to account for at least one sampling error. The method comprises storing data into a storage device and adjusting the location of the data in the storage device to account for synchronization errors.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the comparator output signal.

Abstract: An amplifier includes a first circuit and a second circuit. The first circuit, in a first mode of the amplifier, amplifies an input signal to produce a first output signal. The second circuit is coupled to the first circuit to cause the first circuit to, in a second mode of the amplifier, provide a second output signal that is indicative of a degree of calibration of the amplifier.

Abstract: A number of control signals are provided, where each is responsive to a phase error measured at a different time between a first oscillatory signal and a number of second oscillatory signals. A node is either charged or discharged using a number of charged storage devices, where each device has a predetermined capacitance, in response to the number of first control signals. The method is applicable in frequency control circuit applications such as phase locked loops (PLLs), delay locked loops (DLLs) and clock recovery circuits (CRCs).

Abstract: An embodiment of the invention is directed to a circuit including first and second filter nodes for being connected to a filter and first and second bypass nodes corresponding to the first and second filter nodes, respectively. A charge transfer circuit having at least one charge transfer node is to be alternatively coupled to one of the filter nodes and a corresponding one of the bypass nodes for transferring charge to control a differential voltage of the filter nodes. First and second amplifiers are to buffer the voltages on the first and second filter nodes at first and second outputs which are coupled to the first and second bypass nodes, respectively. The output voltage of each amplifier can be adjusted according to a difference between a control voltage and a common mode voltage of the first and second nodes.

Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one clock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

Abstract: According to an embodiment of the invention, an apparatus is disclosed which includes a phasedetector (PD) that is capable of providing a number of first control signals, where each control signal is responsive to a phase error measured at a different time between a first oscillatory signal and one or more second oscillatory signals. The apparatus further includes a capacitor circuit that is coupled to the PD and has a number of charge storage devices. Each charge storage device has a predetermined capacitance. The capacitor circuit is adapted to provide an amount of charge to a filter node in response to a respective one of the first control signals. A voltage of the filter node is filtered and fed to a controllable oscillator. The one or more second oscillatory signals are derived from the output of the oscillator, thus forming a closed loop frequency control circuit.

Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one dock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes an operational amplifier coupled in a circuit configuration. The circuit configuration includes two transistors coupled to the operational amplifier so that the corresponding voltages at the terminals or ports of the transistors are substantially identical. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes an operational amplifier coupled in a circuit configuration. The circuit configuration includes two circuit components coupled to the operational amplifier so that the corresponding voltages at the terminals or ports of the circuit components are substantially identical. The circuit components include any circuit components capable of implementing a transconductance.

Abstract: An embodiment of the invention is directed to a circuit including first and second filter nodes for being connected to a filter and first and second bypass nodes corresponding to the first and second filter nodes, respectively. A charge transfer circuit having at least one charge transfer node is to be alternatively coupled to one of the filter nodes and a corresponding one of the bypass nodes for transferring charge to control a differential voltage of the filter nodes. First and second amplifiers are to buffer the voltages on the first and second filter nodes at first and second outputs which are coupled to the first and second bypass nodes, respectively. The output voltage of each amplifier can be adjusted according to a difference between a control voltage and a common mode voltage of the first and second nodes.

Abstract: An improved clock recovery circuit is disclosed. A first inverter pulse generator and a second inverter pulse generator for receiving nonreturn-to-zero (NRZ) data and in response thereto generating a signal having a frequency (f) is provided. A differential pair that is coupled to the first and second inverter pulse generators for mixing the signal provided by the pulse generators and a clock signal is provided.

Abstract: An embodiment of the invention is directed to a method of automatically adjusting a common mode output level of a first differential amplifier that is connected to a first digital circuit, in response to variation in a trip point level of a second digital circuit. The second digital circuit includes a replicate of the first digital circuit to generate a trip point level that is equivalent to a trip point level of the first digital circuit. The invention may yield a single-ended digital signal whose duty cycle accurately tracks that of an input differential signal pair in a manner that is substantially independent of fabrication process skew.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the computer output signal.

Abstract: A variable delay cell with a self-biasing load suitable for the implementation of a voltage controlled oscillator and other functions. Because the invention employs current steering between symmetric loads and fully differential voltage control, it is very fast relative to conventional methods and has reduced jitter and improved power supply noise rejection. Additionally, since the load is self-biasing, the need to externally generate a bias current for the load is eliminated. This significantly simplifies design. Also as the load readily self biases in response to changes in the bias current of the biasing transistor, desirable functionalities can be achieved merely by appropriately changing the bias current into the biasing transistor. Notably, the slew rate of both the rising and falling edge can be controlled in this way. Because the load provides a fully differential output, noise immunity as well as a 50% duty cycle is readily achieved.

Abstract: A write control unit, coupled to a memory cell, for controlling write operations to the memory cell is disclosed. The write control unit includes a write qualification unit that qualifies the write operation. The write qualification unit includes a first input for receiving a first data signal that indicates a current data value of the memory cell. The write qualification unit also includes a second input for receiving a second data signal that indicates a data value to be written to the memory cell. The write qualification unit enables a write operation to the memory cell only if the first data signal is different from the second data signal (i.e., the first data value and the second data value are different). If the first data value and the second data value are the same, the write qualification unit suppresses the write operation.

Abstract: A voltage controlled oscillator (VCO) having a current source and a process dependent (or process controlled) impedance is disclosed. The voltage controlled oscillator includes a current mirror that generates a reference current in response to a control current. The reference current is proportional to the control current. The process dependent impedance, which is coupled to the current mirror, compensates the reference current to account for process variations in the manufacture of the (VCO) circuit.