Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: An ice cube machine that generates ice cubes having an alcohol content of at least 2-5%. The ice cube machine operates at temperatures of no greater than 0° F., and typically at least 0° F. or colder. An ice dispensing system monitors the amount of ice cubes dispensed from the machine and can determine the amount of alcohol dispensed from the system.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Abstract: A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.

Abstract: Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Abstract: A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.

Abstract: In an embodiment, an analog voltage recovery circuit comprising a plurality of capacitors having first terminals connected to a node having the analog voltage, and comprising a state machine, where during an operating mode the second terminals of the plurality of capacitors are coupled to a first rail, and where during a digitization mode the state machine couples the second terminals of a set of the plurality of capacitors to a second rail so that the analog voltage is closer to the second rail voltage than during the beginning of the digitization mode. In an embodiment, the analog voltage recovery circuit brings the node voltage to the second rail voltage at the end of the digitization mode, and then floats the node and couples the second terminals of the plurality of capacitors to the first rail to approximately restore the analog voltage. Other embodiments are described and claimed.

Abstract: An embodiment may be described as a switched capacitor analog equalizer circuit with offset voltage cancellation, where an embodiment comprises an amplifier in which a feedback path from its output port to one of its input ports is provided during a reset phase, and where the amplifier's input port connected to the feedback path is also connected to one terminal of an offset-correction capacitor and one terminal of a sampling capacitor. The other terminal of the offset-correction capacitor is connected to a switch and the other terminal of the sampling capacitor is connected to an input port to receive a signal. During the reset phase, the switch is open, and during a sampling phase, the switch is closed so that the offset-correction capacitor and the sampling capacitor are connected in parallel. Other embodiments are described and claimed.

Abstract: A method and apparatus for high-speed serial data recovery. The apparatus comprises providing a storage device to store data and a block to adjust the position of the data in the storage device to account for at least one sampling error. The method comprises storing data into a storage device and adjusting the location of the data in the storage device to account for synchronization errors.

Abstract: In some embodiments an apparatus includes an oscillator and a delay unit to provide a delay in response to an output of the oscillator. The delay unit is to provide an output to be used as a power-on reset signal. Other embodiments are described and claimed.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Abstract: A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.

Abstract: Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Abstract: Communications between a host and a peripheral may be initiated by the peripheral transmitting data at the highest support data rate to the host. If the host is able to recognize the data, the host can so indicate to the peripheral. Otherwise, the peripheral may try a lower data rate progressively decreasing the data rate until the best possible data rate is identified under current conditions. In this way, a communication link may be established in a relatively straightforward fashion that is optimal for the given current conditions.