Patents by Inventor M. Roberts
M. Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200364600Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.Type: ApplicationFiled: December 29, 2017Publication date: November 19, 2020Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Jeanette M. Roberts, James S. Clarke
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Publication number: 20200365656Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.Type: ApplicationFiled: September 28, 2017Publication date: November 19, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Nicole K. Thomas, Abhishek A. Sharma, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, Roman Caudillo, Kanwaljit Singh, James S. Clarke
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Publication number: 20200365688Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.Type: ApplicationFiled: August 7, 2020Publication date: November 19, 2020Applicant: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
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Patent number: 10815933Abstract: A variable area fan nozzle actuation (“VAFN”) system is disclosed. The VAFN system may include an electrohydrostatic actuator (“EHA”) arranged to translate a VAFN panel relative to a translating sleeve. An electrical coupling may extend between a translating sleeve associated with the VAFN system and the fixed structure. The electrical coupling may be movable so that as the translating sleeve and fixed structure move relative to each other, power may be provided to the EHA by a wiring harness extending across the space between the translating sleeve and the fixed structure and connecting the EHA to an EHA power source.Type: GrantFiled: June 22, 2018Date of Patent: October 27, 2020Assignee: Rohr, Inc.Inventor: Stephen M. Roberts
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Patent number: 10807951Abstract: Provided herein, inter alia, are methods and compounds for inhibiting mTORC1 and for treating diseases associated with mTORC1 activity.Type: GrantFiled: October 12, 2018Date of Patent: October 20, 2020Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Daniel K. Nomura, Roberto Zoncu, Allison M. Roberts, Kelvin F. Cho, Yik Sham Clive Chung, Hijai Shin, Benjamin Croze
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Patent number: 10803396Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.Type: GrantFiled: June 19, 2018Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Zachary R. Yoscovits, Roman Caudillo, Ravi Pillarisetty, Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Nicole K. Thomas, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Patent number: 10804399Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.Type: GrantFiled: September 24, 2016Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, Hubert C. George, James S. Clarke
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Publication number: 20200321436Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.Type: ApplicationFiled: December 23, 2017Publication date: October 8, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, Kanwaljit Singh, Roza Kotlyar, Patrick H. Keys, James S. Clarke
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Publication number: 20200312990Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.Type: ApplicationFiled: June 9, 2016Publication date: October 1, 2020Applicant: Intel CorporationInventors: Jeanette M. Roberts, James S. Clarke, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits
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Publication number: 20200312989Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Hubert C. George, Sarah Atanasov, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts, Stephanie A. Bojarski
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Publication number: 20200312963Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Stephanie A. Bojarski, Hubert C. George, Sarah Atanasov, Nicole K. Thomas, Ravi Pillarisetty, Lester Lampert, Thomas Francis Watson, David J. Michalak, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
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Publication number: 20200291085Abstract: Aspects of the disclosure provide fusion proteins that bind cells expressing one or more target molecules including, for example, one or more cell surface multisubunit signaling receptors (e.g.Type: ApplicationFiled: November 26, 2019Publication date: September 17, 2020Applicants: President and Fellows of Harvard College, Dana-Farber Cancer Institute, Inc.Inventors: Jeffrey Charles Way, Avram Lev Robinson-Mosher, Thomas M. Roberts, Jean Zhao
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Publication number: 20200295164Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.Type: ApplicationFiled: January 8, 2018Publication date: September 17, 2020Applicant: Intel CorporationInventors: Kanwaljit Singh, Ravi Pillarisetty, Nicole K. Thomas, Payam Amin, Roman Caudillo, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, James S. Clarke, Lester Lampert, David J. Michalak
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Patent number: 10770545Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.Type: GrantFiled: August 30, 2016Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
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Publication number: 20200279937Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.Type: ApplicationFiled: December 23, 2017Publication date: September 3, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Willy Rachmady, Kanwaljit Singh, Nicole K. Thomas, Hubert C. George, Zachary R. Yoscovits, Roman Caudillo, Payam Amin, Jeanette M. Roberts, James S. Clarke
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Patent number: 10763347Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.Type: GrantFiled: December 14, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Patent number: 10763349Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.Type: GrantFiled: June 29, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, James S. Clarke, Zachary R. Yoscovits, David J. Michalak
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Patent number: 10763420Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.Type: GrantFiled: June 13, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Zachary R. Yoscovits, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, James S. Clarke
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Patent number: 10756202Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.Type: GrantFiled: June 8, 2016Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Adel A. Elsherbini
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Patent number: PP32431Abstract: A new and distinct variety of peach tree (Prunus persica), which is denominated varietally as ‘Wapeachone’ and that produces an attractively colored yellow-fleshed, clingstone peach, which is mature for harvesting and shipment approximately October 12 to October 19 under the ecological conditions prevailing in the San Joaquin Valley of central California.Type: GrantFiled: December 18, 2019Date of Patent: November 10, 2020Assignee: Wawona Packing Co., LLCInventors: John Keith Slaughter, Kaylan M. Roberts