Patents by Inventor Makoto Miura
Makoto Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7842973Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier geneType: GrantFiled: July 13, 2006Date of Patent: November 30, 2010Assignee: Hitachi, Ltd.Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Patent number: 7812805Abstract: To provide a driver circuit that enables reduction in the number of elements formed through a high-voltage process and in chip size. An embodiment of the present invention relates to a driver circuit for inversion-driving a liquid crystal display panel, including: a positive-polarity line transmitting a positive display signal relative to a common electrode signal; a negative-polarity line transmitting a negative display signal relative to the common electrode signal; a dot inversion switch circuit switching the positive-polarity line and the negative-polarity line from each other to be connected with a source line; a charge recovery circuit connected with the positive-polarity line through a positive charge recovery switch and connected with the negative-polarity line through a negative charge recovery switch; and a common short circuit connecting the positive-polarity line and the negative-polarity line with a common electrode.Type: GrantFiled: October 18, 2005Date of Patent: October 12, 2010Assignee: NEC Electronics CorporationInventor: Makoto Miura
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Patent number: 7800601Abstract: Disclosed is a display controlling apparatus including latch circuits for holding color data of a current line and a previous line, a latch circuit for holding a polarity signal of the previous line, and a recovery control circuit. The recovery control circuit controls a recovery switch from color data of the previous and current lines, a polarity signal and a recovery clock. For both driving method employing frame-based common inverting and the driving method employing line-based common inverting, the display/controlling apparatus recovers electric charge efficiently to provide for low power dissipation.Type: GrantFiled: June 26, 2007Date of Patent: September 21, 2010Assignee: NEC Electronics CorporationInventor: Makoto Miura
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Patent number: 7582901Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.Type: GrantFiled: February 17, 2005Date of Patent: September 1, 2009Assignee: Hitachi, Ltd.Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai, Tsuyoshi Ishikawa, Toshiyuki Mine, Makoto Miura
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Patent number: 7521734Abstract: A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.Type: GrantFiled: May 28, 2004Date of Patent: April 21, 2009Assignee: Renesas Technology Corp.Inventors: Eiji Oue, Katsuyoshi Washio, Hiromi Shimamoto, Katsuya Oda, Makoto Miura
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Patent number: 7463231Abstract: The grayscale voltage generating circuit comprises an input/driving stage circuit amplifying an input voltage and output stage circuits receiving a output voltage from the input/driving stage circuit, outputting one of the grayscale voltages, and having a capacitor to keep a voltage level of the grayscale voltage. The output stage circuits are sequentially switched to be connected with the input/driving stage circuit, and an output voltage from the input/driving stage circuit is fed to the plurality of output stage circuits in order. Each of the output stage circuits outputs the grayscale voltage based on a voltage held in the capacitor irrespective of connection with the input/driving stage circuit.Type: GrantFiled: August 24, 2005Date of Patent: December 9, 2008Assignee: Nec Electronics CorporationInventor: Makoto Miura
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Patent number: 7388030Abstract: The present invention provides a method for suppressing hemolytic anemia by selectively ameliorating reticulocyte increase and iron deposition on spleen caused as the side effects of methionine. The present invention also provides an appetite suppressor with reduced such side effects, where threonine is used as the effective ingredient of the suppressor of hemolytic anemia due to methionine and a combination of methionine and threonine is used as the effective ingredient of the appetite suppressor.Type: GrantFiled: May 24, 2004Date of Patent: June 17, 2008Assignee: Ajinomoto Co., Inc.Inventors: Yasuko Kawamata, Takeshi Kimura, Makoto Miura, Sakino Toue, Ryousei Sakai
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Patent number: 7368763Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.Type: GrantFiled: March 7, 2005Date of Patent: May 6, 2008Assignee: Hitachi, Ltd.Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
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Publication number: 20080001941Abstract: Disclosed is a display controlling apparatus including latch circuits for holding color data of a current line and a previous line, a latch circuit for holding a polarity signal of the previous line, and a recovery control circuit. The recovery control circuit controls a recovery switch from color data of the previous and current lines, a polarity signal and a recovery clock. For both driving method employing frame-based common inverting and the driving method employing line-based common inverting, the display/controlling apparatus recovers electric charge efficiently to provide for low power dissipation.Type: ApplicationFiled: June 26, 2007Publication date: January 3, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Makoto Miura
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Patent number: 7214973Abstract: A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.Type: GrantFiled: March 3, 2005Date of Patent: May 8, 2007Assignee: Hitachi, Ltd.Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Patent number: 7095043Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.Type: GrantFiled: March 2, 2004Date of Patent: August 22, 2006Assignee: Hitachi, Ltd.Inventors: Katsuya Oda, Nobuyuki Sugii, Makoto Miura, Isao Suzumura, Katsuyoshi Washio
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Publication number: 20060169987Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.Type: ApplicationFiled: March 7, 2005Publication date: August 3, 2006Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
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Patent number: 7071500Abstract: A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.Type: GrantFiled: June 15, 2004Date of Patent: July 4, 2006Assignee: Renesas Technology Corp.Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Patent number: 7049890Abstract: An operational amplifier comprises: differential input stages to which differential signals can be inputted with full operating range; current source circuits coupled to determine current values of the differential input stages, phase inverter circuits which are provided between transistors of an output stage circuit and the current source circuits; a driver stage circuit and the output stage circuit. The phase inverter circuits control currents of the current source circuits depending on the output signal potential level. By using this structure, it becomes possible to realize a high slew rate throughout the full operating range.Type: GrantFiled: April 6, 2005Date of Patent: May 23, 2006Assignee: NEC Electronics CorporationInventor: Makoto Miura
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Publication number: 20060103618Abstract: To provide a driver circuit that enables reduction in the number of elements formed through a high-voltage process and in chip size. An embodiment of the present invention relates to a driver circuit for inversion-driving a liquid crystal display panel, including: a positive-polarity line transmitting a positive display signal relative to a common electrode signal; a negative-polarity line transmitting a negative display signal relative to the common electrode signal; a dot inversion switch circuit switching the positive-polarity line and the negative-polarity line from each other to be connected with a source line; a charge recovery circuit connected with the positive-polarity line through a positive charge recovery switch and connected with the negative-polarity line through a negative charge recovery switch; and a common short circuit connecting the positive-polarity line and the negative-polarity line with a common electrode.Type: ApplicationFiled: October 18, 2005Publication date: May 18, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Makoto Miura
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Publication number: 20060050036Abstract: The grayscale voltage generating circuit comprises an input/driving stage circuit amplifying an input voltage and output stage circuits receiving a output voltage from the input/driving stage circuit, outputting one of the grayscale voltages, and having a capacitor to keep a voltage level of the grayscale voltage. The output stage circuits are sequentially switched to be connected with the input/driving stage circuit, and an output voltage from the input/driving stage circuit is fed to the plurality of output stage circuits in order. Each of the output stage circuits outputs the grayscale voltage based on a voltage held in the capacitor irrespective of connection with the input/driving stage circuit.Type: ApplicationFiled: August 24, 2005Publication date: March 9, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Makoto Miura
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Publication number: 20060043418Abstract: A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.Type: ApplicationFiled: March 3, 2005Publication date: March 2, 2006Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Patent number: 6987420Abstract: An operational amplifier comprises: differential input stages to which differential signals can be inputted with full operating range; current source circuits coupled to determine current values of the differential input stages, phase inverter circuits which are provided between transistors of an output stage circuit and the current source circuits; a driver stage circuit and the output stage circuit. The phase inverter circuits control currents of the current source circuits depending on the output signal potential level. By using this structure, it becomes possible to realize a high slew rate throughout the full operating range.Type: GrantFiled: September 29, 2003Date of Patent: January 17, 2006Assignee: NEC Electronics CorporationInventor: Makoto Miura
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Publication number: 20050212082Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.Type: ApplicationFiled: February 17, 2005Publication date: September 29, 2005Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai, Tsuyoshi Ishikawa, Toshiyuki Mine, Makoto Miura
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Patent number: 6943594Abstract: In a driver, a voltage-follower-type operational amplifier receives current input data to generate an output signal. A transient state detecting circuit detects a transient state in the current input data to generate a first pulse signal when the current input data is increased and generate a second pulse signal when the current input data is decreased. A switch circuit substantially increases corresponding load currents flowing through the voltage-follower-type operational amplifier in accordance with the first and second pulse signals.Type: GrantFiled: April 15, 2004Date of Patent: September 13, 2005Assignee: NEC Electronics CorporationInventor: Makoto Miura