Patents by Inventor Malcolm S. Ware

Malcolm S. Ware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9292662
    Abstract: A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 9146608
    Abstract: A method, computer program product, and apparatus for managing power management in a data processing system are presented. A core is activated and configured to operate at a frequency in response to a request to increase a processing capacity. A determination whether a use of power resulting from activating the core meets a policy for the use of the power is made. A set of parameters is adjusted to meet the policy for the use of power in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed by a set of cores is made. An indication that the request to increase the processing capacity is unavailable is made in response to the number of operations having not increased.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Andreas Bieswanger, Andrew J. Geissler, Hye-Young McCreary, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 9026818
    Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 5, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Heather L. Hanson, Charles Robert Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8909383
    Abstract: A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Scott J. Hadderman, Daniel J. Kearney, Wei Huang, K. Paul Muller, William J. Rooney, Guillermo J. Silva, Malcolm S. Ware, Emmanuel Yashchin, Peter B. Yocom
  • Patent number: 8832479
    Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 8707074
    Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Heather L. Hanson, Charles R. Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Publication number: 20140101471
    Abstract: A method, computer program product, and apparatus for managing power management in a data processing system are presented. A core is activated and configured to operate at a frequency in response to a request to increase a processing capacity. A determination whether a use of power resulting from activating the core meets a policy for the use of the power is made. A set of parameters is adjusted to meet the policy for the use of power in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed by a set of cores is made. An indication that the request to increase the processing capacity is unavailable is made in response to the number of operations having not increased.
    Type: Application
    Filed: December 12, 2013
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas Bieswanger, Andrew J. Geissler, Hye-Young McCreary, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 8683160
    Abstract: An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Karthick Rajamani, Gregory S. Still, Jeffrey A. Stuecheli, Malcolm S. Ware
  • Patent number: 8677160
    Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8650367
    Abstract: An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Guy L. Guthrie, Karthick Rajamani, Gregory A. Still, Jeffrey A. Stuecheli, Malcolm S. Ware
  • Patent number: 8645640
    Abstract: An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Guy L. Guthrie, Karthick Rajamani, Gregory S. Still, Jeffrey A. Stuecheli, Malcolm S. Ware
  • Patent number: 8635478
    Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Chase, Joshua D. Friedrich, Andrew J. Geissler, Soraya Ghiasi, Norman K. James, Jagat V. Pokala, Malcolm S. Ware
  • Patent number: 8627124
    Abstract: A technique for performing storage power management on storage subsystems includes measuring, using a power measurement device, power consumption of a storage subsystem. A first average power and a second average power for the storage subsystem are calculated based on the measured power consumption. In this case, the first average power is calculated over a shorter time period than the second average power. One or more first actuators are incremented in response to the first average power of the storage subsystem being greater than a first power level to reduce the first average power of the storage subsystem below the first power level within a first time period. One or more second actuators are incremented in response to the second average power of the storage subsystem being greater than a second power level and less than the first power level to reduce the second average power of the storage subsystem below the second power level within a second time period that is greater than the first time period.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Wesley M. Felter, Anthony N. Hylick, Malcolm S. Ware
  • Patent number: 8627128
    Abstract: A method, computer program product, and apparatus for managing power in a data processing system are presented. A core is activated in the data processing system and configured to operate at a frequency in response to receiving a request to increase a processing capacity of a set of resources in the data processing system. A determination whether a use of power resulting from activating the core configured to operate at the frequency meets a policy for the use of the power in the data processing system is made. A set of parameters associated with devices in the set of resources are adjusted to meet the policy for the use of power in the data processing system in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed per unit of time by a set of cores associated with the set of resources increased after activating the core is made.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Andreas Bieswanger, Andrew J. Geissler, Hye-Young McCreary, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 8595721
    Abstract: A mechanism is provided for temporarily allocating dedicated processors to a shared processor pool. A virtual machine monitor determines whether a temporary allocation associated with an identified dedicated processor is long-term or short-term. Responsive to the temporary allocation being long-term, the virtual machine monitor determines whether an operating frequency of the identified dedicated processor is within a predetermined threshold of an operating frequency of one or more operating systems utilizing the shared processor pool. Responsive to the operating frequency of the identified dedicated processor failing to be within the predetermined threshold, the virtual machine monitor either increases or decreases the frequency of the identified dedicated processor to be within the predetermined threshold of the operating frequency of the one or more operating systems utilizing the shared processor pool and temporarily allocates the identified dedicated processor to the shared processor pool.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Naresh Nayar, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8589556
    Abstract: A mechanism is provided for allocating energy budgets to a plurality of logical partitions. An overall energy budget for the data processing system and a total of a set of requested initial energy budgets for the plurality of partitions are determined. A determination is made as to whether the total of the set of requested initial energy budgets for the plurality of partitions is greater than the overall energy budget for the data processing system. Responsive to the total of the set of requested initial energy budgets exceeding the overall energy budget, an initial energy budget is allocated to each partition in the plurality of partitions based on at least one of priority or proportionality of each partition in the plurality of partitions such that a total of the initial energy budgets for the plurality of partitions does not exceed the overall energy budget of the data processing system.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Heather L. Hanson, Charles R. Lefurgy, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 8566618
    Abstract: Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Karthick Rajamani, Juan C. Rubio, Malcolm S. Ware
  • Patent number: 8527801
    Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bishop C. Brock, John B. Carter, Alan J. Drake, Michael S. Floyd, Charles R. Lefurgy, Malcolm S. Ware
  • Publication number: 20130166095
    Abstract: A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott J. Hadderman, Daniel J. Kearney, Wei Huang, K. Paul Muller, William J. Rooney, Guillermo J. Silva, Malcolm S. Ware, Emmanuel Yashchin, Peter B. Yocom
  • Patent number: 8463456
    Abstract: A mechanism is provided for minimizing system power in a data processing system. A management control unit determines whether a convergence has been reached in the data processing system. If convergence fails to be reached, the management control unit determines whether a maximum fan flag is set to indicate that a fan is operating at a maximum speed. Responsive to the maximum fan flag failing to be set, a thermal threshold of the data processing system is either increased or decreased and thereby a fan speed of the data processing system is either increased or decreased based on whether the system power of the data processing system has either increased or decreased and based on whether a temperature of the data processing system has either increased or decreased. Thus, a new thermal threshold and a new fan speed are formed. The process is then repeated until convergence has been met.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Elmootazbellah N. Elnozahy, Malcolm S. Ware, Wei Huang