Abstract: A mechanism is provided for directed resource folding for power management. The mechanism receives a set of static platform characteristics and a set of dynamic platform characteristics for a set of resources associated with the data processing system thereby forming characteristic information. The mechanism determines whether one or more conditions have been met for each resource in the set of resources using the characteristic information. Responsive to the one or more conditions being met, the mechanism performs a resource optimization to determine at least one of a first subset of resources in the set of resources to keep active and a second subset of resources in the set of resources to dynamically fold. Based on the resource optimization, the mechanism performs either a virtual resource optimization to optimally schedule the first subset of resources or a physical resource optimization to dynamically fold the second subset of resources.

Abstract: A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval.

Abstract: A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element.

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

Abstract: A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element.

Abstract: An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.

Abstract: An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.

Abstract: An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.

Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

Abstract: Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements.

Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

Abstract: A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element.

Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.

Abstract: A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.

Abstract: A technique for performing storage power management on storage subsystems includes measuring, using a power measurement device, power consumption of a storage subsystem. A first average power and a second average power for the storage subsystem are calculated based on the measured power consumption. In this case, the first average power is calculated over a shorter time period than the second average power. One or more first actuators are incremented in response to the first average power of the storage subsystem being greater than a first power level to reduce the first average power of the storage subsystem below the first power level within a first time period. One or more second actuators are incremented in response to the second average power of the storage subsystem being greater than a second power level and less than the first power level to reduce the second average power of the storage subsystem below the second power level within a second time period that is greater than the first time period.

Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.

Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

Abstract: A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value.