Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: An optical pickup for a recording medium includes a light source, an objective lens, a main photodetector, and a front photodetector. The configuration of the optical pickup enables converging or diverging of light to be incident on a plate beam splitter so that light can be received at an effective light receiving region of a front photodetector without interference due to internal reflection occurring in the plate beam splitter. In the alternative, a wedge beam splitter in the optical pickup includes first and second mirror planes at a predetermined angle to transmit and reflect incident light at a predetermined ratio. In the optical pickup, an amount of light that is exactly proportional to an output power of the light source can be detected, where the output power of the light source can be accurately controlled, thereby improving a linearity of the output power of the light source.

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract: At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.

Abstract: A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off.

Abstract: A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. The first pull-up transistor is connected between an external power supply terminal and an output terminal and responds to a first control signal which swings between an internal power supply voltage and a ground voltage. The external power supply terminal receives an external power supply having a voltage level higher than the voltage level of the internal power supply. The first pull-up transistor provides an output signal to the output terminal having the voltage level of the internal power supply voltage minus a predetermined voltage drop. The second pull-up transistor is connected between the internal power supply voltage terminal and the output terminal.

Abstract: A data traffic processing method in a subscriber network access subsystem of an advanced communications processing system is disclosed including an operation process of a data processing master module and an operation process of a data processing slave module. The operation process of the data processing master module includes the steps of: initializing hardware, displaying a system logo on a screen and initializing all parameters; initializing the data processing master module; and initializing a slave and informing a service processing board assembly (SPA) that a master execution preparation has been ended. The operation process of the data processing slave module includes the steps of: initializing the hardware and displaying the system logo on the screen; initializing the data processing slave module; and informing a master that the slave is an alive state and initializing a protocol parameter.

Abstract: A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled.

Abstract: The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line.

Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Abstract: A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

Abstract: An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with each bank including at least two rows of memory cells. Each of the data lines extends along one of the columns of memory cells so that each of the data lines extends along memory cells from each of the banks of memory cells. The memory cell selector includes a row decoder which selects one of the plurality of rows, a column decoder which selects one of the plurality of columns, and a bank decoder which selects one of the banks. The connector connects one of the memory cells to a respective data line in response to the memory cell selector. Accordingly, data from only one of the memory cells is provided on a respective one of the data lines at any point and time.

Abstract: An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.

Abstract: A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

Abstract: In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.

Abstract: A back-bias level sensor used for a semiconductor device wherein a sensing current for sensing a back-bias voltage is prevented from directly flowing into the substrate (or the back-bias voltage terminal). The gate of a PMOS transistor is provided with the back-bias voltage while the source is provided with a ground voltage, so that a pump circuit performs the pumping operation to increase the back-bias voltage when the back-bias voltage is lower than a predetermined voltage level; otherwise, the pump circuit is de-energized, thereby reducing the back-bias voltage.