Abstract: The apparatus, systems, and methods described herein may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

Abstract: Apparatus, systems, and methods described herein may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: Provided are a system and method for informing a vehicle accident using a telematics device. In an emergency, such as vehicle collision, etc., the system and method propagate information on the accident to vehicles around the accident scene, thereby informing the vehicles of traffic congestion. Since the vehicles continuously inform the same to vehicles behind through ad-hoc communication, a vehicle guided by a telematics device can recognize the traffic congestion ahead, re-search for a path, and thereby make a detour. Therefore, although vehicles behind the accident scene cannot see the occurrence of the accident on a foggy highway, etc., the risk of a chain-reaction crash is reduced. In addition, it is possible to avoid traffic congestion due to an accident in downtown.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: Provided is a network global positioning system (GPS) terminal. The network GPS terminal includes: a GPS receiver receiving GPS data; a GPS processor processing the received GPS data to a predetermined form; a network communication part communicating with an external apparatus through a network in order to receive a request for the GPS data from the external apparatus, and transmit the processed GPS data to the external apparatus in response to the request; a security access controller authenticating the external apparatus; and a network management part managing connection information and security information of the external apparatus, the network communication part simultaneously communicating with at least one external apparatus using a TCP/IP protocol. A method of providing GPS data using a network is also provided.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A method, apparatus and system are described which provide a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: An optical signal converter and a method or controlling an amplification gain according to a rotating speed of an optical disc. An optical signal detector detects an optical signal reflected from an optical disc in a reproduction mode and converts the detected optical signal into an electrical signal. A gain control signal generator generates a gain control signal when a voltage level of a driving signal used to drive the optical disc exceeds a maximum output voltage of the optical signal converter. A gain switcher selects an amplification gain of the optical signal converter in response to the gain control signal and an external control signal. A signal amplifier amplifies a signal output from the optical signal detector in response to an output signal of the gain switcher.

Abstract: An optical pickup for a recording medium includes a light source, an objective lens, a main photodetector, and a front photodetector. The configuration of the optical pickup enables converging or diverging of light to be incident on a plate beam splitter so that light can be received at an effective light receiving region of a front photodetector without interference due to internal reflection occurring in the plate beam splitter. In the alternative, a wedge beam splitter in the optical pickup includes first and second mirror planes at a predetermined angle to transmit and reflect incident light at a predetermined ratio. In the optical pickup, an amount of light that is exactly proportional to an output power of the light source can be detected, where the output power of the light source can be accurately controlled, thereby improving a linearity of the output power of the light source.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: A rotor for use in an induction motor includes a main body installed to be rotatable by having a gap inside a stator, providing a flow path of magnetic fluxes produced from the coil, and including a plurality of conductors formed on an edge region of the main body; a pair of barriers formed to pass through the main body in a manner to have a semi-spherical shape from a sectional view, base lines of the semi-spherical shape being disposed to face each other; and a plurality of permanent magnets disposed inside the individual barriers. Therefore, the permanent magnets can be easily affixed to the inner side of the individual barriers, and the loss of the magnetic fluxes is minimized, thereby improving the efficiency of the rotor.