Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: The present invention relates to an alginate sponge and a preparation method thereof, more particularly to an alginate sponge having significantly improved flexibility, structural integrity, water-absorptivity, and processability, to be used for medical and tissue engineering purposes, and a simple preparation method thereof. The alginate sponge of the present invention has a maximum bend angle (flexibility) of at least 90°?, an apparent density (structural integrity) ranging from 0.006 to 0.1 glcm3, and a saline solution absorption ratio ranging from 150 to 700%.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: A resource allocation device includes a database of user and service information, a resource allocation management unit for determining whether a service request agrees with a service level agreement and whether it accepts a resource allocation request, a service level agreement unit for negotiating the service level agreement with the user, sending the received service request to the resource allocation management unit, acquiring the result of the resource allocation request, and transmitting the result of the resource allocation request to the user, a routing information management unit for obtaining a network configuring information, storing the network configuring information in the database, discovering the path to provide the service and storing the discovered path in the database to be reused and a policy control management unit for deciding a policy according to whether the service request and the resource allocation request are accepted.

Abstract: The present invention relates to a method of continuously producing a phosphor at a supercritical water (SCW) condition and an apparatus used in the method. A phosphor produced according to the method of the present invention has similar luminosity to a phosphor produced according to a conventional solid-state method and the size and shape of particles thereof is also uniform. Accordingly, a phosphor according to the method of the present invention is applicable in various fields such as plasma display (PDP) and field emission display (FED). Also, in the method of producing a phosphor according to the present invention, the total reaction time is within about one minute, which is shorter than in the solid-state method. Also, since a separate heat processing process is not needed to obtain crystallized particles, it is efficient in aspects of time and energy.

Abstract: An outer rotor type motor includes a rotor housing having a bottom portion and a sidewall upwardly extending from and an outer peripheral edge of the bottom portion, and a shaft bushing having a base and a hollow shaft-insertion portion provided at a center of the base. The base of the shaft bushing is coupled at the bottom portion of the rotor housing by an insert molding. A driving shaft is fitted in the shaft-insertion portion of the shaft bushing. A plurality of blade holes are circumferentially formed in the bottom portion of the rotor housing, and a plurality of blades are formed by an insert molding such that the blades are disposed at one edges of the respective blade holes in the bottom portion along a radial direction.

Abstract: A rotor of an outer-rotor type motor includes a rotor case made of a metal and provided with a base plate, an insert hole formed in a center portion of the base plate, a shaft bushing, for coupling a rotational axle and the rotor case, fixedly inserted into the insert hole by a insert molding, and a plurality of protruding ribs fixedly connected to the base plate. And the protruding ribs are radially connected to the shaft bushing.

Abstract: An outer rotor type motor includes a rotation shaft installed in a bearing housing; a stator formed of a field winding; a rotor disposed outside the stator to house the stator and having a yoke surface on which a permanent magnet for performing a magnetic interaction with the field winding of the stator, the rotor rotating around the stator; and a shaft bushing for connecting the rotor and the rotation shaft. The shaft bushing is insert-molded at a central portion of the rotor to be connected with the rotor.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract: An optical signal converter and a method or controlling an amplification gain according to a rotating speed of an optical disc. An optical signal detector detects an optical signal reflected from an optical disc in a reproduction mode and converts the detected optical signal into an electrical signal. A gain control signal generator generates a gain control signal when a voltage level of a driving signal used to drive the optical disc exceeds a maximum output voltage of the optical signal converter. A gain switcher selects an amplification gain of the optical signal converter in response to the gain control signal and an external control signal. A signal amplifier amplifies a signal output from the optical signal detector in response to an output signal of the gain switcher.

Abstract: A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.