Patents by Inventor Manabu Matsumoto

Manabu Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9543271
    Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu Matsumoto, Akira Tanimoto, Isao Ozawa
  • Publication number: 20160372159
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Patent number: 9449316
    Abstract: Provided is a settlement terminal device including a plurality of information processing units. The settlement terminal device includes a first information processing unit, a secure second information processing unit, and an orientation detection unit which detects a direction of the settlement terminal device with respect to gravity. The first information processing unit reflects a detection result of the orientation detection unit on an orientation of a first display content displayed on the first display unit, and the second information processing unit determines whether or not to reflect the detection result of the orientation detection unit on an orientation of a second display content, in accordance with the second display content displayed on the second display unit. Thereby, a settlement terminal device capable of easily performing an input operation and display confirmation in a settlement process is provided.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Manabu Matsumoto
  • Publication number: 20160268229
    Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
    Type: Application
    Filed: August 27, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu MATSUMOTO, Akira TANIMOTO, Isao OZAWA
  • Patent number: 9437533
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Publication number: 20160236881
    Abstract: Provided is a conveyance system for an object and for conveying the object to a container mounted on a chassis of a trailer. The conveyance system includes a jack device that lifts the chassis from below, and a stage device arranged behind the jack device. The stage device includes a conveyance body on which the object is placed and conveyed, a stage on which the conveyance body travels, a mobile body supporting the stage and capable of movement in a front-back direction of the chassis, and a jack mechanism provided to the mobile body and that raises the stage from below to lift or lower the stage. The mobile body moves forward and the jack mechanism lowers the stage while the jack device raises the chassis, and the conveyance body travels on floor faces of the stage and the container in this state to convey the object to the container.
    Type: Application
    Filed: November 22, 2013
    Publication date: August 18, 2016
    Applicant: TOYOTA STEEL CENTER CO., LTD.
    Inventors: Nobuaki ITO, Manabu MATSUMOTO
  • Patent number: 9418359
    Abstract: A settlement terminal device of this disclosure includes a settlement processing unit that performs a settlement process and a power supply unit that supplies power stored in a battery to the settlement processing unit. The settlement processing unit detects in advance a state where a battery residual capacity is equal to or less than a predetermined value when performing the settlement process, and sets a first detection threshold value for a first settlement mode requiring a first power consumption level which is greater than a second detection threshold value for a second settlement mode requiring a second power consumption level which is lower than the first power consumption level.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 16, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Manabu Matsumoto
  • Publication number: 20160172016
    Abstract: According to one embodiment, a semiconductor device includes, for example, a circuit board, a plurality of elements, a plurality of controllers, and a first signal line. The elements are provided on the circuit board. The elements each include a memory. The controllers each are configured to control read of data from the memory. The controllers each are configured to control write of data into the memory. A control signal is transmitted through the first signal line. The first signal line is used in common by the controllers.
    Type: Application
    Filed: March 10, 2015
    Publication date: June 16, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Manabu MATSUMOTO, Katsuya MURAKAMI, Koichi NAGAI
  • Publication number: 20160151995
    Abstract: The present invention is an interlayer film for laminated glass that includes 2 or more resin layers laminated on each other. The interlayer film for laminated glass has a large number of recesses and a large number of protrusions on at least one surface thereof. The recesses each have a groove shape with a continuous bottom. The recesses adjacent to each other are parallel to each other and regularly arranged in a line.
    Type: Application
    Filed: August 1, 2014
    Publication date: June 2, 2016
    Applicant: Sekisui Chemical Co., Ltd.
    Inventors: Hirofumi KITANO, Hiroaki INUI, Taiki KATAYAMA, Manabu MATSUMOTO, Kazuhiko NAKAYAMA
  • Publication number: 20160151996
    Abstract: The present invention aims to provide a vehicular windshield having a laminated glass structure in which an interlayer film for laminated glass is interposed between at least a pair of glass plates, which contains few air bubbles remaining between the glass plates and the interlayer film for laminated glass to have an excellent appearance and is less likely to cause ghosting when external rays of light are seen through the vehicular windshield.
    Type: Application
    Filed: August 1, 2014
    Publication date: June 2, 2016
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Hirofumi KITANO, Manabu MATSUMOTO, Kazuhiko NAKAYAMA
  • Patent number: 9355999
    Abstract: A semiconductor device includes: a substrate having an insulating resin and a metal pattern provided on the insulating resin; a mounted component mounted on the metal pattern; and an epoxy resin encapsulating the metal pattern and the mounted component, wherein a slit is provided in the metal pattern around the mounted component, and the insulating resin exposed from the metal pattern and the epoxy resin are brought into intimate contact with each other in the slit.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 31, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Masumoto, Hiroshi Kawata, Manabu Matsumoto, Yoshitaka Otsubo
  • Publication number: 20160129674
    Abstract: The present invention aims to provide an interlayer film for laminated glass including two or more resin layers laminated together which exhibits excellent deaeration properties in the production process of a laminated glass and prevents ghosting, and a laminated glass including the interlayer film for laminated glass.
    Type: Application
    Filed: August 1, 2014
    Publication date: May 12, 2016
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Hirofumi KITANO, Manabu MATSUMOTO, Kazuhiko NAKAYAMA
  • Publication number: 20160101602
    Abstract: The present invention aims to provide an interlayer film for laminated glass including two or more resin layers laminated together which exhibits excellent deaeration properties in the production process of a laminated glass and prevents ghosting, and a laminated glass including the interlayer film for laminated glass. The present invention relates to an interlayer film for laminated glass including at least two resin layers laminated together, the interlayer film having a large number of recesses and a large number of projections on at least one surface, the recesses having a groove shape with a continuous bottom and being regularly arranged adjacently in parallel with one another, the surface with the large number of recesses and the large number of projections having a groove depth (Rzg) of the recesses determined in conformity with JIS B-0601(1994) of 10 to 40 ?m, the recesses each having an interval from an adjacent recess of 1000 to 1500 ?m.
    Type: Application
    Filed: August 1, 2014
    Publication date: April 14, 2016
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Hirofumi KITANO, Manabu MATSUMOTO, Kazuhiko NAKAYAMA
  • Patent number: 9312215
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Publication number: 20160071821
    Abstract: A semiconductor device includes: a substrate having an insulating resin and a metal pattern provided on the insulating resin; a mounted component mounted on the metal pattern; and an epoxy resin encapsulating the metal pattern and the mounted component, wherein a slit is provided in the metal pattern around the mounted component, and the insulating resin exposed from the metal pattern and the epoxy resin are brought into intimate contact with each other in the slit.
    Type: Application
    Filed: June 2, 2015
    Publication date: March 10, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki MASUMOTO, Hiroshi KAWATA, Manabu MATSUMOTO, Yoshitaka OTSUBO
  • Publication number: 20160050330
    Abstract: A user is enabled to make different selection as to whether or not to include a blank page for each data processing. A storage portion stores setting information indicating whether or not to perform data processing of image data with a blank page excluded for each data processing, and a control portion judges whether or not each data processing is processing performed with a blank page of the image data excluded based on the setting information stored in the storage portion, and executes first data processing which is judged as processing performed with the blank page excluded by excluding the blank page as well as executes second data processing which is judged as processing performed without excluding the blank page concurrently with the first data processing by including the blank page.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Inventors: Kazushi YAMANEKI, Manabu MATSUMOTO, Kazuma OGAWA
  • Publication number: 20150380061
    Abstract: A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.
    Type: Application
    Filed: March 2, 2015
    Publication date: December 31, 2015
    Inventors: Manabu MATSUMOTO, Isao OZAWA
  • Patent number: 9203983
    Abstract: A user is enabled to make different selection as to whether or not to include a blank page for each data processing. A storage portion stores setting information indicating whether or not to perform data processing of image data with a blank page excluded for each data processing, and a control portion judges whether or not each data processing is processing performed with a blank page of the image data excluded based on the setting information stored in the storage portion, and executes first data processing which is judged as processing performed with the blank page excluded by excluding the blank page as well as executes second data processing which is judged as processing performed without excluding the blank page concurrently with the first data processing by including the blank page.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 1, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazushi Yamaneki, Manabu Matsumoto, Kazuma Ogawa
  • Publication number: 20150324615
    Abstract: An information processing device includes a first information processing unit that is accommodated in a housing, and in which a first input display section is provided on an operational surface of the housing, and a tamper-resistant secure second information processing unit that is accommodated in front of the first information processing unit in the housing gripped by an operator, and in which a second input display section is provided in front of the first input display section on the operational surface. Further, in the information processing device, for example, a secure state display section that indicates a secure mode in authentication input, or indicates a non-secure mode in a case other than the authentication input is disposed on the operational surface. Even when a secure portion and a non-secure portion are present together, security of authentication information is secured, and an operator's mistake or an incorrect operation is suppressed.
    Type: Application
    Filed: May 7, 2015
    Publication date: November 12, 2015
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Manabu MATSUMOTO, Kazuki SAITOH, Takeshi NINOMIYA, Yoshihide NAKASHIMA, Seiro SHIMODA
  • Patent number: D764424
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu Matsumoto, Isao Ozawa