Patents by Inventor Manabu Takei

Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770582
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai
  • Patent number: 10770581
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoki Kumagai
  • Patent number: 10693002
    Abstract: In an n-type current diffusion region, a first p+-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p+-type region is provided between adjacent trenches, separated from the first p+-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p+-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p+-type regions. The third p+-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p+-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 23, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Naoyuki Ohse, Shinsuke Harada, Manabu Takei
  • Patent number: 10629725
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoyuki Ohse
  • Publication number: 20200083368
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Application
    Filed: July 22, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA, Naoki KUMAGAI
  • Publication number: 20200083369
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.
    Type: Application
    Filed: July 22, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai
  • Patent number: 10522673
    Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Patent number: 10347005
    Abstract: A carrier for carrying an object includes a fork that is vertically movable to carry the object and that is able to be inserted into an opening of a flat portion of the object, a sensor that obtains actual measured values at a plurality of points on the flat portion of the object, and an object state identification device that identifies, based on the actual measured values, an object state including at least one of a position and a posture of the object with respect to the sensor.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 9, 2019
    Assignees: MURATA MACHINERY, LTD., UMEMURA EDUCATIONAL INSTITUTIONS
    Inventors: Masaomi Iida, Manabu Hashimoto, Shoichi Takei
  • Publication number: 20190165163
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 30, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA, Naoyuki OHSE
  • Patent number: 10297683
    Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei, Akio Nakagawa
  • Publication number: 20190109228
    Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.
    Type: Application
    Filed: August 30, 2018
    Publication date: April 11, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA
  • Publication number: 20190074373
    Abstract: In an n-type current diffusion region, a first p30-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p30-type region is provided between adjacent trenches, separated from the first p30-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p30-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p30-type regions. The third p30-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p30-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Naoyuki Ohse, Shinsuke Harada, Manabu Takei
  • Patent number: 10186610
    Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 22, 2019
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Publication number: 20180358463
    Abstract: On a front surface of a semiconductor base, a first n?-type drift region and a second n-type drift region are provided. A gate trench is provided that penetrates an n+-type source region and p-type base region, and reaches the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region and the p-type base region, and reaches a p-type semiconductor region, through the second n-type drift region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at a bottom and corners of the contact trench, and forms a Schottky junction with the second n-type drift region at side walls of the contact trench. A depth of the contact trench is a depth by which a mathematical area of a part thereof forming the Schottky junction is a predetermined mathematical area or greater.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 13, 2018
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke KOBAYASHI, Naoyuki OHSE, Shinsuke HARADA, Manabu TAKEI
  • Patent number: 10128369
    Abstract: In a trench-gate vertical MOSFET, an n-type drift layer and p-type base layer are epitaxially grown on an n+ silicon carbide substrate, and an n++ source region and p++ contact region are provided inside the p-type base layer. The first source electrode contacts the n++ source region, and the second source electrode contacts the p++ contact region. The first source electrode and second source electrode are separated from each other.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Manabu Takei, Ryuji Yamada
  • Patent number: 10103256
    Abstract: A semiconductor device, including a first groove, a second groove and a first impurity region provided on a semiconductor substrate, a second impurity region provided in the first impurity region, a gate electrode provided in the first groove, a first insulating film provided between the first groove and the gate electrode, a second insulating film provided in the second groove, and a third insulating film provided astride tops of the first groove and the second groove. Each of the first and second insulating films has a lower half portion that is thicker than an upper half portion thereof. The lower half portions of the first and second insulating films are connected. The gate electrode has first and second portions thereof respectively contacting the lower and upper half portions of the first insulating film, a width of the first portion being narrower than a width of the second portion.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 16, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei
  • Patent number: 10094867
    Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 9, 2018
    Assignees: FUJI ELECTRIC CO., LTD., National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsuru Sometani, Manabu Takei, Shinsuke Harada
  • Patent number: 10032866
    Abstract: In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle ?3 of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle ?1 of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Publication number: 20180182847
    Abstract: In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle ?3 of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle ?1 of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.
    Type: Application
    Filed: November 1, 2017
    Publication date: June 28, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA
  • Publication number: 20180182884
    Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 28, 2018
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke KOBAYASHI, Manabu Takei, Shinsuke Harada