Patents by Inventor Manabu Takei

Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100079423
    Abstract: A data acquisition circuit sets one of the potential value at one end of a signal line and the value of a current flown thereto when one end of a current path of a drive device is connected to a light emitting device with the other end thereof set to a potential value where no current flows to the light emitting device. Then the circuit causes current to flow via the current path and the signal line and acquires one of the value of the current flown to the signal line and the potential value at the one end of the signal line according to the set value. A correction operation circuit acquires a threshold voltage and a current amplification factor of the drive device based on one of the current and potential values thus acquired as well as on one of the potential and current values thus set.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Manabu Takei, Jun Ogura, Shunji Kashiyama, Tsuyoshi Ozaki
  • Patent number: 7638368
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: December 29, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Michio Nemoto, Manabu Takei, Tatsuya Naito
  • Publication number: 20090317959
    Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 24, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Manabu TAKEI
  • Patent number: 7601597
    Abstract: A manufacturing method for a super-junction semiconductor device is disclosed. The method includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a base region(s) of the other conductivity type and source regions of the one conductivity type to be used for formation of MOS gate structures; a third step of forming, by anisotropic vapor-phase etching using an insulating film mask, trenches that penetrate through the base region(s) and reach the low-resistivity semiconductor substrate or its vicinity; and a fourth step of burying epitaxial layers of the other conductivity type in the respective trenches, the first to fourth steps being executed in this order.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 13, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20090206398
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Application
    Filed: April 21, 2009
    Publication date: August 20, 2009
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Koh YOSHIKAWA, Akio SUGI, Kouta TAKAHASHI, Manabu TAKEI, Haruo NAKAZAWA, Noriyuki IWAMURO
  • Patent number: 7572683
    Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: August 11, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Manabu Takei, Tatsuya Naito, Michio Nemoto
  • Patent number: 7569431
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: August 4, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Patent number: 7535059
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: May 19, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Patent number: 7518393
    Abstract: A pixel circuit flows a current having a current value corresponding to a test voltage without intervening any display element.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: April 14, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Manabu Takei
  • Patent number: 7511419
    Abstract: A luminescent panel includes a transparent substrate, a first transparent electrode provided on the transparent substrate, a luminescent layer provided on the first transparent electrode, and a second transparent electrode provided on the luminescent layer. A reflecting film provided on the second electrode, reflects light emitted from the luminescent layer through the second transparent electrode and causes the reflected light to outwardly emit from the transparent substrate.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: March 31, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Manabu Takei, Tomoyuki Shirasaki
  • Patent number: 7498733
    Abstract: A display panel includes a transistor array substrate which has a plurality of transistors including at least a driving transistor, and a plurality of pixel electrodes electrically connected to the driving transistor of the plurality of transistors. A plurality of light-emitting layers are provided on the pixel electrodes. A counter electrode is provided on the light-emitting layers. Each of a plurality of interconnections is arranged between the pixel electrodes adjacent to each other and electrically connected to the counter electrode.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: March 3, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Satoru Shimoda, Manabu Takei, Tomoyuki Shirasaki, Jun Ogura
  • Patent number: 7499006
    Abstract: A driver circuit for driving optical elements which is applied to a pixel driver circuit of the display device in this invention comprises a first current path with one end connected to the optical elements and the other end connected to a drive power supply; a second current path electrically connected to the first current path; a write-in control circuit which flows the write-in current having a predetermined current value in the direction of the other end side from the one end side of the first current path via the second current path; a charge storage circuit which stores the electric charge accompanying the write-in current flowing in the first current path; a drive control circuit which supplies the drive current to the optical elements via the first current path has a current value corresponding to the current value of the write-in current and drives these optical elements based on the electric charge stored in the charge storage circuit; and has a first timing operation in which the electric charge of
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: March 3, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Kazuhito Sato, Tsuyoshi Ozaki, Manabu Takei
  • Publication number: 20080290805
    Abstract: A display panel (110) includes a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a non-selection time (Tnse), and a current storage circuit (Tr1, Tr3, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the non-selection time (Tnse).
    Type: Application
    Filed: February 21, 2008
    Publication date: November 27, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventors: Hiroyasu YAMADA, Manabu Takei
  • Patent number: 7420322
    Abstract: A display device includes a flat display panel in which a plurality of pixels are arrayed in a matrix at an interval and covered with an optically transparent material, and an optical sheet to impart the front directivity of the flat display panel. Light which is emitted from a predetermined one of the plurality of pixels and emerges outside from the surface of the optical sheet located on a region except the pixel to the front direction overlaps neighboring pixels arranged around the pixel in a width equal to or smaller than 20% of the pixel width of the neighboring pixels.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: September 2, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Manabu Takei, Tomoyuki Shirasaki
  • Publication number: 20080153212
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Application
    Filed: February 4, 2008
    Publication date: June 26, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Manabu TAKEI
  • Publication number: 20080102582
    Abstract: A manufacturing method for a super-junction semiconductor device is disclosed. The methods includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a base region(s) of the other conductivity type and source regions of the one conductivity type to be used for formation of MOS gate structures; a third step of forming, by anisotropic vapor-phase etching using an insulating film mask, trenches that penetrate through the base region(s) and reach the low-resistivity semiconductor substrate or its vicinity; and a fourth step of burying epitaxial layers of the other conductivity type in the respective trenches, the first to fourth steps being executed in this order.
    Type: Application
    Filed: September 13, 2007
    Publication date: May 1, 2008
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Manabu Takei
  • Patent number: 7355571
    Abstract: A display panel (110) includes a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a nonselection time (Tnse), and a current storage circuit (Tr1, Tr3, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the nonselection time (Tnse).
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: April 8, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Yamada, Manabu Takei
  • Patent number: 7355263
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 8, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20070292995
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Michio NEMOTO, Manabu TAKEI, Tatsuya NAITO
  • Patent number: 7307330
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: December 11, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Michio Nemoto, Manabu Takei, Tatsuya Naito