Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract: A method for forming semiconductor devices includes placing a laminar structure having electrically insulating material arranged between a plurality of electrically conductive structures onto a surface of a semiconductor wafer comprising a plurality of semiconductor device structures. An electrically conductive structure of the plurality of electrically conductive structures is located adjacent to a semiconductor device structure of the plurality of semiconductor device structures. Each electrically conductive structure of the plurality of electrically conductive structures extends from a first surface of the laminar structure towards a second opposite surface of the laminar structure.

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract: An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract: In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.

Abstract: An electrical component that includes a substrate and a polymeric layer oriented in working relation with the substrate, the polymeric layer including a low molecular mass polyimide.

Abstract: A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements.

Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Abstract: Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

Abstract: A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier.

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Abstract: A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the first face. The first contact pad is an external contact pad. The device further includes a first contact clip attached to the second face of the first power semiconductor chip. A second power semiconductor chip is attached to the first contact clip, and a second contact clip is attached to the second power semiconductor chip.

Abstract: An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.

Abstract: Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.