Patents by Inventor Manfred Schneegans
Manfred Schneegans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11424201Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.Type: GrantFiled: June 19, 2018Date of Patent: August 23, 2022Assignee: Infineon Technologies AGInventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
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Patent number: 11239188Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.Type: GrantFiled: November 20, 2017Date of Patent: February 1, 2022Assignee: Infineon Technologies AGInventors: Markus Zundel, Rainer Pelzer, Manfred Schneegans
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Patent number: 10734352Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.Type: GrantFiled: October 1, 2018Date of Patent: August 4, 2020Assignee: Infineon Technologies AGInventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
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Patent number: 10648096Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided.Type: GrantFiled: November 23, 2015Date of Patent: May 12, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Werner Robl, Michael Melzl, Manfred Schneegans, Bernhard Weidgans, Franziska Haering
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Patent number: 10651140Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.Type: GrantFiled: August 10, 2018Date of Patent: May 12, 2020Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
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Patent number: 10373868Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.Type: GrantFiled: January 18, 2016Date of Patent: August 6, 2019Assignees: INFINEON TECHNOLOGIES AUSTRIA AG, TECHNISCHE UNIVERSITAET GRAZInventors: Martin Mischitz, Markus Heinrici, Michael Roesner, Oliver Hellmund, Caterina Travan, Manfred Schneegans, Peter Irsigler, Friedrich Kroener
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Patent number: 10340227Abstract: In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.Type: GrantFiled: March 16, 2016Date of Patent: July 2, 2019Assignee: Infineon Technologies AGInventors: Markus Zundel, Manfred Schneegans
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Publication number: 20190103378Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.Type: ApplicationFiled: October 1, 2018Publication date: April 4, 2019Inventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
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Publication number: 20180366427Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.Type: ApplicationFiled: June 19, 2018Publication date: December 20, 2018Inventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
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Publication number: 20180350761Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Inventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
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Patent number: 10090265Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.Type: GrantFiled: June 24, 2016Date of Patent: October 2, 2018Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
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Publication number: 20180145045Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Inventors: Markus Zundel, Rainer Pelzer, Manfred Schneegans
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Patent number: 9929111Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.Type: GrantFiled: March 17, 2017Date of Patent: March 27, 2018Assignee: Infineon Technologies AGInventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
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Patent number: 9911686Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.Type: GrantFiled: May 16, 2016Date of Patent: March 6, 2018Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Andreas Meiser, Martin Mischitz, Michael Roesner, Michael Pinczolits
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Patent number: 9887170Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.Type: GrantFiled: May 11, 2017Date of Patent: February 6, 2018Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Bernhard Weidgans, Franziska Haering
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Publication number: 20170317042Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.Type: ApplicationFiled: May 11, 2017Publication date: November 2, 2017Inventors: Manfred Schneegans, Bernhard Weidgans, Franziska Haering
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Patent number: 9780053Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.Type: GrantFiled: November 15, 2015Date of Patent: October 3, 2017Assignee: Infineon Technologies AGInventors: Magdalena Hoier, Peter Scherl, Manfred Schneegans
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Publication number: 20170207123Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.Type: ApplicationFiled: January 18, 2016Publication date: July 20, 2017Inventors: Martin MISCHITZ, Markus HEINRICI, Michael ROESNER, Oliver HELLMUND, Caterina TRAVAN, Manfred SCHNEEGANS, Peter IRSIGLER, Friedrich KROENER
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Publication number: 20170194272Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.Type: ApplicationFiled: March 17, 2017Publication date: July 6, 2017Inventors: Martin MISCHITZ, Markus HEINRICI, Barbara EICHINGER, Manfred SCHNEEGANS, Stefan KRIVEC
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Patent number: 9666546Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.Type: GrantFiled: April 28, 2016Date of Patent: May 30, 2017Assignee: Infineon Technologies AGInventors: Manfred Schneegans, Bernhard Weidgans, Franziska Haering