Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: A device for treating wafers on assembly carriers is disclosed. A wafer to be treated can be fixed on a liquid film that is located between the front side of the wafer and the assembly carrier by freezing of the film.

Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.

Abstract: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad.

Abstract: A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method.

Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.

Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.

Abstract: A method of electrically interconnecting a semiconductor chip to another electronic device including providing a carrier including contact pins and a chip attached to the carrier, the chip having a copper contact pad that faces away from the carrier, extending a copper electrical connector between the contact pins and the contact pad, and diffusion soldering the copper electrical connector to the active area with a solder material including tin to form a solder connection including a contiguous bronze coating disposed between and in direct contact with both the copper electrical connector and the contact pad.

Abstract: A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method.

Abstract: An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad.

Abstract: A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method.

Abstract: A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method.