Abstract: The present invention provides a CMOS GOA circuit. The first NOR gate (Y1) and the second NOR gate (Y2) are located in the input control module (1). The two input ends of the first NOR gate (Y1) respectively receives the stage transfer signal (Q(N?1)) of the GOA unit circuit of the former stage and the global signal (Gas), and the two input ends of the second NOR gate (Y2) respectively receives the first clock signal (CK1) and the global signal (Gas). When the global signal (Gas) is high voltage level, the all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, both the first NOR gate (Y1) and the second NOR gate (Y2) are controlled to output low voltage levels to control the inverted stage transfer signal (XQ(N)) to be high voltage level.

Abstract: The present invention provides a CMOS GOA circuit. The latch module (3) comprises a NOR gate (Y), and the two input ends of the NOR gate (Y) are respectively inputted with the inverted stage transfer signal (XQ(N)) and the global signal (Gas). When the global signal (Gas) is high voltage level, all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate (Y) is controlled to pull down voltage levels of the stage transfer signals (Q(N)) of the respective stages to clear and reset the stage transfer signals (Q(N)) of the respective stages. In comparison with prior art, an independent reset module is not required.

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.

Abstract: A baseplate circuit is disclosed. The baseplate comprises an IC region, a plurality of WOA regions, a plurality of GOA regions, and a plurality of switches. Each WOA region comprises a plurality of baseplate conducting wires, each of the baseplate conducting wires is electrically connected with the IC region. Each GOA region comprises a plurality of gate lines, each of the gate lines is electrically connected with one of the baseplate conducting wires. Each of the switches is used to electrically connect one of the gate lines and one of the baseplate conducting wires.

Abstract: A GOA circuit and LCD are disclosed. The GOA circuit includes cascaded GOA units and a control module. Each of the GOA units is driven by a first level of transfer clock, a second level of transfer clock, a first control clock and a second control clock to charge horizontal signal lines corresponding to a display area. The control module masks the first level of transfer clock and the second level of transfer clock when all of the horizontal signal lines are charged completely by the GOA circuit, such that the gate driving signals on the horizontal signal lines are discharged until the level equals to the predetermined level. In this way, the horizontal signal lines are prevented from generating redundant pulse signals before the first gate driving signals are outputted, which ensures the normal operations of the GOA circuit.

Abstract: The present invention proposes a TFT, an array substrate, and a method of forming a TFT. The TFT includes a substrate, a buffer layer, a patterned poly-si layer, an isolation layer, a gate layer, and a source/drain pattern layer. The poly-si layer includes a heavily doped source and a heavily doped drain, and a channel. The gate layer includes a first gate area and a second gate area. The source/drain pattern layer includes a source pattern, a drain pattern and a bridge pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting the heavily doped drain, and one end of the bridge pattern connecting the first gate area and the second gate area. The driving ability of the present inventive TFT is enhanced without affecting the leakage current.

Abstract: A GOA substrate includes GOA circuit units connected in cascade. The GOA circuit unit includes an output module, a reset module, a latch module, and an input module. The output module is used for outputting the scan signal based on a trigger signal. The reset module is used for resetting the trigger signal based on the reset signal. The latch module is used to hold and pull down the electric potential of the trigger signal. The input module is used for receiving the scan signal outputted by the previous stage GOA circuit unit. The input module includes a first CMOS transmission gate and a first transistor. The input module can lower the equivalent on-resistance of the transistor, elevate the drive current between the input terminal and the output terminal, so to increase level transmission speed, lower drive power loss of the transistor and improve the stability of the circuit.

Abstract: A GOA circuit includes GOA circuit units. When scan signal outputted by a previous stage GOA circuit unit and a next stage GOA circuit unit are at a low level, a fifth transistor controlled by the scan signal of previous stage GOA circuit unit and a sixth transistor controlled by the scan signal of a next stage GOA circuit unit turn on, so that the current stage GOA circuit unit starts to operate, and voltage of a control node becomes the same as the first constant voltage. When a third clock signal is triggered, the scan signal of the previous stage GOA circuit unit is charged from the low level, which was maintained previously, to the first constant voltage. Therefore, scan signal of GOA circuit unit will not affect the normal stage transmission of other GOA circuit units, and mitigate the problem of outputting redundant scan signal pulse.

Abstract: The disclosure discloses a GOA circuit based on the LTPS, including a modulation circuit; a charging circuit; an input signal terminal and an output signal terminal. The modulation circuit and the charging circuit are connected to the input signal terminal and the output signal terminal to make the modulation circuit and the charging circuit in parallel connection, and the charging circuit is used to charge the output scanning signal during the mutation process to increase the mutation speed of the output scanning signal. Wherein the charging circuit is a switch including a control terminal, a first terminal, and a second terminal; the input signal terminal is connected to the first terminal of the charging circuit. The output signal terminal is connected to the second terminal and the control terminal of the charging circuit separately. A display apparatus including the GOA circuit based on the LTPS is also provided.

Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.

Abstract: A gate drive circuit and a display device are provided. The present disclosure pertains to the technical field of display technology and solves the technical problem of wide frame of the existing display device. The shifting register is configured to output primary drive signal into a first follower and a second follower in consecutive first scanning period t1 and second scanning period t2. The first follower is configured to output gate drive signal to a first gate line in t1 under the driving of the primary drive signal; and the second follower is configured to output the gate drive signal to a second gate line in t2 under the driving of the primary drive signal. The present disclosure can be applied to display devices, such as liquid crystal display devices and OLED display devices, and the like.

Abstract: A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.

Abstract: A display panel and thin film transistor array substrate are provided. The thin film transistor array substrate includes an active area and a peripheral region. The thin film transistor array substrate further includes a base substrate, a light shield metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first signal line layer, a second signal line layer, a third signal line layer, a third insulating layer, a fourth insulating layer, a common line layer, a fifth insulating layer, and a pixel electrode layer. The present invention prevents display failure problems caused by the signal line being disconnected.

Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.

Abstract: A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.

Abstract: A scan driving circuit is disclosed for executing a driving operation for cascaded scan lines and includes a pull-down control module, a pull-down module, a reset control module, a reset module, a down-stream module, a first bootstrap capacitor, a constant low-level voltage source utilized, and a constant high-level voltage source. The whole structure of the disclosed scan driving circuit is simple, and power consumption is low.

Abstract: A scan driving circuit is provided for driving scan lines which are connected in series, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transmitting module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. The entire structure of the scan driving circuit is simple, and energy consumption is reduced.

Abstract: The present invention discloses a liquid crystal driving circuit, comprising the first to fifth electric switches and the first to fourth capacitors. The first and second capacitors are in the main area, and the third and fourth capacitors are in the sub area. The first to third capacitors are coupled in series. The first and second capacitors, the third and fourth capacitors are respectively coupled in parallel between the first and second electric switches and the common voltage end. The fourth and fifth electric switches are coupled in series between the data end and the second electric switch. The first to fourth electric switches are controlled with the gate control end. The data end is respectively coupled to the first, second and fourth electric switches.

Abstract: A GOA (Gate On Array) circuit applied to a liquid crystal display device is disclosed. The liquid crystal display device has a plurality of scan lines, The GOA circuit has a plurality of cascaded GOA units. An (N)th level GOA unit controls charge to an (N)th level scanning line. The (N)th level GOA unit includes a forward-reward scan circuit, a pull-up circuit, an bootstrap capacitor circuit, a pull-up control circuit, and a pull-down sustain circuit. The pull-up circuit, the bootstrap capacitor circuit, the pull-up control circuit, and the pull-down sustain circuit are connected with a gate signal point. The forward-reward scan circuit is connected with an (N?1)th level scanning line and an (N+1)th level scanning line, so as to raise the stability of the gate signal point and reduce the usages of thin film transistors.