Abstract: A scan driving circuit, and an array substrate and a display panel having the scan driving circuit are disclosed. The scan driving circuit includes a plurality of cascaded scan driving units. Each scan driving unit includes an input unit and an output unit. The input unit receives the activation trigger signal, transmits to the output unit and controls the output units in a scanning state. The scan driving unit includes a scan signal modulation unit having at least two transistors. The transistors output a clock modulation signal according to a plurality of clock signals. The clock modulation signal includes at least two first voltages separated with predetermined duration. The output unit outputs scan driving signal from the scan signal output end according to the clock modulation signal. The scan signal includes two sub-scan signals to control pixel unit to receive image data within a scan cycle.

Abstract: The disclosure provides a scan driving circuit and a flat display device, the scan driving circuit includes a plurality of cascaded scan driving units, each of the scan driving units includes a forward/backward scanning circuit, applied to receive and process a superior level transmitted signal and a first inferior level transmitted signal, so as to control the scan driving circuit to scan forward and backward; an input circuit charges a pull-up control signal point and a pull-down control signal point according to the superior level transmitted signal and the first inferior level transmitted signal; a latch circuit latches the superior level transmitted signal and the first inferior level transmitted signal; a reset circuit clears and resets electric potential of the pull-up control signal point; a signal multiplexing circuit processes a same level transmitted signal, a second inferior level transmitted signal and latch data.

Abstract: The present disclosure relates to a gate driving circuit and the LCD thereof. The input circuit generates second control signals in accordance with up-level normal-phase scanning driving signals, up-level inverting-phase scanning driving signals, and first control signals outputted by the latch circuit. The reset and control circuit generates third control signals in accordance with reset signals, the first control signals, and the second control signals.

Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.

Abstract: The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of cascaded scan drivers, each of the scan drivers includes a forward/backward scanning circuit, an output circuit, a pull-down circuit and a pull-down control circuit, the forward/backward scanning circuit is configured to control the scan drivers to scan forward or backward, the output circuit outputs a first scanning signal, a second scanning signal and a third scanning signal. The first scanning signal, the second scanning signal and the third scanning signal are output by sharing the forward/backward scanning circuit, the pull-down circuit and the pull-down control circuit according to the disclosure, which can reduce the amount of thin film transistors of the scan driving circuit and spare space that are further beneficial for narrow frame design.

Abstract: The present disclosure relates to a scanning driving circuit including a plurality of cascaded-connected scanning driving units. Each of the scanning driving unit includes a forward-backward scanning circuit, a first and a second input circuit outputting first and second input signals; a pull-down circuit outputting first or second pull-down signals and pulling down or charging a first pull-down control signal point or a second pull-down control signal point; a first and a second control circuit charging or pulling down the first pull-down control signal point or the second pull-down control signal point; and the first and the second output circuit generating the first and the second scanning driving signals for the first and the second scanning line to drive pixel cells.

Abstract: A liquid crystal panel driving circuit and a liquid crystal display device are provided. Every three sub-pixel unit columns are defined as a row cycle that comprises a first data line, a second data line, and a third data line coupled to a same data driving signal output line of the data driver via the switch unit. The switch unit is configured to control the first data line, the second data line, and the third data line to output data signals in different output orders.

Abstract: A scan driving circuit is disclosed for executing a driving operation for cascaded scan lines and includes a pull-down control module, a pull-down module, a reset control module, a reset module, a down-stream module, a first bootstrap capacitor, a constant low-level voltage source utilized, and a constant high-level voltage source. The whole structure of the disclosed scan driving circuit is simple, and power consumption is low.

Abstract: A GOA circuit includes GOA circuit units. A holding module is substituted for a capacitor in each GOA circuit unit. A second transistor in the holding module is turned on when a scanning signal does not produce a pulse so that voltage imposed in a first control node is held by a first transistor and a third transistor. Because the transistors form a passage between the first control node and a first constant voltage, the voltage imposed on the first control node does not vary due to electricity leakage. Because a second capacitor is coupled with the first control node, the pulse of the scanning signal output by the GOA circuit unit reaches to an ideal high voltage level. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.

Abstract: A gate driver on array (GOA) circuit includes a plurality of stages of GOA units cascaded. A first control latch module, a signal processing module, and a second control latch module of an Nth stage GOA unit generate an Nth stage dipulse gate driving signal and an Nth stage cascade signal according to clock signals, and an (N?2)th or (N+2)th stage cascade signal. For the clock signals corresponding to adjacent two stages of the GOA units, a first clock signal is delayed for a predetermined period of time with respect to a second clock signal. The two dipulse gate driving signals generated by the adjacent two stages of the GOA units partially overlap.

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.

Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.

Abstract: The present disclosure relates to a display panel including a first substrate, a second substrate, a liquid crystal layer between the first substrate and the second substrate, a masking layer on the first substrate, a buffering layer arranged on the masking layer and the first substrate, a first semiconductor layer on the buffering layer, and an active layer on the first semiconductor layer and the buffering layer. The present disclosure also relates to a display device. With such configuration, the leakage current of the TFTs may be reduced, which also reduces the cross-talk and the flicker of the liquid crystal panel.

Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N?2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.

Abstract: The present disclosure relates to a scanning driving circuit including a plurality of cascaded-connected scanning driving units. Each of the scanning driving unit includes a forward-backward scanning circuit, a first and a second input circuit outputting first and second input signals; a pull-down circuit outputting first or second pull-down signals and pulling down or charging a first pull-down control signal point or a second pull-down control signal point; a first and a second control circuit charging or pulling down the first pull-down control signal point or the second pull-down control signal point; and the first and the second output circuit generating the first and the second scanning driving signals for the first and the second scanning line to drive pixel cells.

Abstract: The present invention provides a scan driving circuit utilized to drive cascading scan lines. The scan driving circuit comprises a pull-down control module, a pull-down module, a reset control module, a reset module, a lower transmission module, a first bootstrap capacitor, a constant low voltage source, and a constant high voltage source. By use of the deployment of the reset module, the scan driving circuit of the present invention improves the stability of the scan driving circuit and meanwhile, the structure of the whole scan driving circuit is simplified.

Abstract: The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of cascaded scan drivers, each of the scan drivers includes a forward/backward scanning circuit, an output circuit, a pull-down circuit and a pull-down control circuit, the forward/backward scanning circuit is configured to control the scan drivers to scan forward or backward, the output circuit outputs a first scanning signal, a second scanning signal and a third scanning signal. The first scanning signal, the second scanning signal and the third scanning signal are output by sharing the forward/backward scanning circuit, the pull-down circuit and the pull-down control circuit according to the disclosure, which can reduce the amount of thin film transistors of the scan driving circuit and spare space that are further beneficial for narrow frame design.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N?2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.