Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.

Abstract: A gate driving circuit is disclosed. The output circuit is connected with the input circuit and the pulling circuit at a first node, responding to scanning driving signal of previous stage to set the pulling circuit in a first status, using a first reference voltage level to set the first node at a first voltage, and held. The output circuit outputs scanning driving signal of current stage according to a first clock signal. The stabilizing circuit is connected with the pulling circuit at a second node, using the first reference voltage level to set the second node at the first voltage, and held. The pulling control circuit responds to a second clock signal to set the pulling circuit in a second status, using a second reference voltage level to pull voltages of the first and second nodes and to hold the voltages. Accordingly, a current leakage can be reduced.

Abstract: A GOA circuit includes GOA circuit units. A holding module is substituted for a capacitor in each GOA circuit unit. A second transistor in the holding module is turned on when a scanning signal does not produce a pulse so that voltage imposed in a first control node is held by a first transistor and a third transistor. Because the transistors form a passage between the first control node and a first constant voltage, the voltage imposed on the first control node does not vary due to electricity leakage. Because a second capacitor is coupled with the first control node, the pulse of the scanning signal output by the GOA circuit unit reaches to an ideal high voltage level. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.

Abstract: The invention provides a GOA circuit for narrow border LCD panel, by disposing a first node leakage prevention unit (700) comprised of ninth TFT (T9), tenth TFT (T10) and third capacitor (C3), wherein the ninth TFT (T9) has gate and source connected to the output clock signal (CK) to form a diode structure to charge the third capacitor (C3) and fourth node (H(n)) to high voltage; the tenth TFT (T10) clears the fourth node during stage-propagated signal duration to ensure normal charging for the first node (Q(n)). The GOA circuit is applicable to dual-side progressive scanning architecture and also to dual-side interlaced scanning architecture, and able to prevent current leakage in the first node under dual-side interlaced scanning architecture to ensure stable operation of circuit and improve reliability of GOA circuit. Moreover, with only two clock signals on each side, the invention is suitable for narrow border display panel.

Abstract: The present disclosure relates to scanning driving circuit and flat display device. A pull-up maintaining module receives clock signals at the previous level, to charge a pull-up control signal node and pull up a pull-down control signal node; a control module receives pull-up control signals at the previous level and scanning driving signals at the previous level, and control the pull-up maintaining module; an output module connects to the pull-up maintaining module and the control module for outputting the scanning driving signals to scanning lines; the scanning lines transmits the scanning driving signals to pixel cells.

Abstract: A gate driving circuit and a liquid crystal display are disclosed. The gate driving circuit includes: an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output buffering circuit electrically connected with the signal processing circuit. Wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel. Each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the two switch modules. The present invention through disposing two switch modules and crosswise connecting the control terminals of the switching tubes, the stress degrees applied on the two switching transistors are the same so as to greatly increase the stability of the circuit operation.

Abstract: A scan driving circuit is provided for driving scan line in cascade, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transferring module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. By disposing the resetting module, the scan driving circuit of the present invention raises the reliability of the scan driving circuit and simplifies the entire structure of the scan driving circuit.

Abstract: The present invention provides a GOA circuit and a liquid crystal display device. The GOA circuit adds the stage transfer unit (900) and the stage transfer pull-down unit (800) and modifying the global control auxiliary unit (1000) to use the stage transfer end (ST(N)) of the stage transfer unit (900) to output the signal which is different from the scan driving signal to be the stage transfer signal and to use the global control auxiliary unit (1000) to stable the voltage level of the stage transfer end (ST(N)) in the period that the output ends (G(N)) of all the GOA units output the scan driving signal at the same time, the signal outputted by the stage transfer end (ST(N)) is opposite to the voltage level of the scan driving signal.

Abstract: A baseplate circuit is disclosed. The baseplate comprises an IC region, a plurality of WOA regions, a plurality of GOA regions, and a plurality of switches. Each WOA region comprises a plurality of baseplate conducting wires, each of the baseplate conducting wires is electrically connected with the IC region. Each GOA region comprises a plurality of gate lines, each of the gate lines is electrically connected with one of the baseplate conducting wires. Each of the switches is used to electrically connect one of the gate lines and one of the baseplate conducting wires.

Abstract: The present invention provides a demultiplex type display driving circuit, including: a plurality of drive units. Each drive unit comprises three demultiplex modules, and each demultiplex module includes two switch elements. The first switch element and the second switch element are controlled to be alternately on with the first branch control signal and the second branch control signal. The third branch control signal controls the two switch elements of the second and the third demultiplex modules to be alternately on to sequentially input the data signal to the first, the second, the third and the fourth data lines. Thus, division one to four of the data signal can be achieved with the three branch control signals. In comparison with prior art, the amount of the branch control signals is decreased, and meanwhile, the CMOS transmission gate is employed to be the switch element in the demultiplex modules.

Abstract: The present invention provides a CMOS GOA circuit. The latch module (3) comprises a NOR gate (Y), and the two input ends of the NOR gate (Y) are respectively inputted with the inverted stage transfer signal (XQ(N)) and the global signal (Gas). When the global signal (Gas) is high voltage level, all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate (Y) is controlled to pull down voltage levels of the stage transfer signals (Q(N)) of the respective stages to clear and reset the stage transfer signals (Q(N)) of the respective stages. In comparison with prior art, an independent reset module is not required.

Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.

Abstract: A gate drive circuit and a display device are provided. The present disclosure pertains to the technical field of display technology and solves the technical problem of wide frame of the existing display device. The shifting register is configured to output primary drive signal into a first follower and a second follower in consecutive first scanning period t1 and second scanning period t2. The first follower is configured to output gate drive signal to a first gate line in t1 under the driving of the primary drive signal; and the second follower is configured to output the gate drive signal to a second gate line in t2 under the driving of the primary drive signal. The present disclosure can be applied to display devices, such as liquid crystal display devices and OLED display devices, and the like.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A GOA circuit and an LCD are disclosed. The GOA circuit includes multiple cascaded GOA units and a control module. Each of the multiple cascaded GOA units is used for charging a corresponding horizontal scanning line in a display area through driving of a first stage-transferring clock, a second stage-transferring clock, a first control clock and a second control clock. The control module is used to control the gate driving signals to be reset to the first voltage level, that is an ineffective voltage level, after the GOA circuit finishes a charging for all of the horizontal scanning lines simultaneously through the starting pulse signal such that a redundant pulse signal generated on the horizontal scanning lines before the gate driving signal of the first stage GOA unit is outputted is avoided in order to ensure a normal operation of the GOA circuit.

Abstract: A scanning-driving circuit and a liquid crystal display device are disclosed. The scanning-driving circuit has a forward-backward scanning module to output a forward and backward scanning-driving signals; a pull-up holding module connected to the forward-backward scanning module to receive a selecting signal of the forward-backward scanning module and to pull up a voltage level of a pull-down control signal node; an input module connected to the forward-backward scanning module and the pull-up holding module to receive a previous-stage clock signal and to charge a pull-up control signal node; a control module connected to the pull-up holding module to receive a present-stage clock signal and to control the pull-up holding module; an output module connected to the pull-up holding module and the control module to output a scanning-driving signal to a scanning line, and to transmit the scanning-driving signal to a pixel unit to ensure a stability of the scanning-driving circuit.

Abstract: The invention provides a scanning driving circuit and a liquid crystal display apparatus. The scanning driving circuit including a latch module to receive and calculate an upper level control signal, a first and a second clock signal and a reset signal to get a first control signal, and latch and output the first control signal; a logic control module receive and calculate the first and the second control signal and the third clock signal to get a logic control signal, and output the logic control signal; an output module receive and calculate the logic control signal and the second control signal to get and output a scanning driving signal, and a scan line connected to the output module to transmit the scanning driving signal to a pixel unit and to achieve the special function of the liquid crystal display apparatus.

Abstract: A scan driving circuit is provided for driving scan line in cascade, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transferring module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. By disposing the resetting module, the scan driving circuit of the present invention raises the reliability of the scan driving circuit and simplifies the entire structure of the scan driving circuit.