Abstract: The present disclosure relates to scanning driving circuit and flat display device. A pull-up maintaining module receives clock signals at the previous level, to charge a pull-up control signal node and pull up a pull-down control signal node; a control module receives pull-up control signals at the previous level and scanning driving signals at the previous level, and control the pull-up maintaining module; an output module connects to the pull-up maintaining module and the control module for outputting the scanning driving signals to scanning lines; the scanning lines transmits the scanning driving signals to pixel cells.

Abstract: The invention disclosure a GOA circuit and a liquid crystal display. The GOA circuit including an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection, the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor. The first voltage limited transistor, and the second filter transistor a reconnected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit. By this design, the damage from the large static electricity to the GOA sub circuit can be avoided.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A GOA substrate includes GOA circuit units connected in cascade. The GOA circuit unit includes an output module, a reset module, a latch module, and an input module. The output module is used for outputting the scan signal based on a trigger signal. The reset module is used for resetting the trigger signal based on the reset signal. The latch module is used to hold and pull down the electric potential of the trigger signal. The input module is used for receiving the scan signal outputted by the previous stage GOA circuit unit. The input module includes a first CMOS transmission gate and a first transistor. The input module can lower the equivalent on-resistance of the transistor, elevate the drive current between the input terminal and the output terminal, so to increase level transmission speed, lower drive power loss of the transistor and improve the stability of the circuit.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: The disclosure provides a scan driving circuit and a flat display device, the scan driving circuit includes a plurality of cascaded scan driving units, each of the scan driving units includes a forward/backward scanning circuit, applied to receive and process a superior level transmitted signal and a first inferior level transmitted signal, so as to control the scan driving circuit to scan forward and backward; an input circuit charges a pull-up control signal point and a pull-down control signal point according to the superior level transmitted signal and the first inferior level transmitted signal; a latch circuit latches the superior level transmitted signal and the first inferior level transmitted signal; a reset circuit clears and resets electric potential of the pull-up control signal point; a signal multiplexing circuit processes a same level transmitted signal, a second inferior level transmitted signal and latch data.

Abstract: A testing circuit includes at least one sub-circuit. The sub-circuit includes a first input end, at least one second input end, at least one third input end, and at least one driving output end. The first switch unit includes controllable switches. The second switch unit includes sub-units and first inverters. The sub-unit includes transmission gates. The control end of the controllable switch connects to the second input end, the first end connects to the first input end, and the second end connects to the input end of the transmission gate. The first control end of the transmission gate connects to the third input end and the input end of the first inverter, the second control end connects to the output end of the first inverter, the output end connects to the driving output end.

Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.

Abstract: The present invention provides a GOA circuit applied for the In Cell type touch display panel. The third transmission gate (TG3) comprising the second P-type thin film transistor (T2) and the third N-type thin film transistor (T3), the first P-type thin film transistor (T1) and the fourth N-type thin film transistor (T4) are added in the output buffer module (600), and the touch control signal (TCK) and the inverted touch control signal (XTCK) are introduced to control the working status of the output buffer module (600). Thus, in the touch scan stage, the third transmission gate (TG3) is deactivated, and the first, the fourth thin film transistors (T1, T4) are activated, and the gate scan driving signal output end (Gate(N)) is floating, and similarly jumps between high, low voltage levels along with that the touch scan driving signal jumps between high, low voltage levels.

Abstract: The present invention provides a demultiplex type display driving circuit, including: a plurality of drive units. Each drive unit comprises three demultiplex modules, and each demultiplex module includes two switch elements. The first switch element and the second switch element are controlled to be alternately on with the first branch control signal and the second branch control signal. The third branch control signal controls the two switch elements of the second and the third demultiplex modules to be alternately on to sequentially input the data signal to the first, the second, the third and the fourth data lines. Thus, division one to four of the data signal can be achieved with the three branch control signals. In comparison with prior art, the amount of the branch control signals is decreased, and meanwhile, the CMOS transmission gate is employed to be the switch element in the demultiplex modules.

Abstract: A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.

Abstract: The present invention provides a scanning driving circuit for executing a driving operation to cascaded scanning lines, the scanning driving circuit includes a pull-down control module, a pull-down module, a reset module, a down link module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source; wherein a cascading manner of the clock signal is determined according to a scanning order of the scanning driving circuit, for the reset module to pull up the corresponding scanning signal of the scanning line. The structure of the scanning driving circuit of the present invention is simple and highly dependable.

Abstract: The invention provides a GOA circuit for narrow border LCD panel, by disposing a first node leakage prevention unit (700) comprised of ninth TFT (T9), tenth TFT (T10) and third capacitor (C3), wherein the ninth TFT (T9) has gate and source connected to the output clock signal (CK) to form a diode structure to charge the third capacitor (C3) and fourth node (H(n)) to high voltage; the tenth TFT (T10) clears the fourth node during stage-propagated signal duration to ensure normal charging for the first node (Q(n)). The GOA circuit is applicable to dual-side progressive scanning architecture and also to dual-side interlaced scanning architecture, and able to prevent current leakage in the first node under dual-side interlaced scanning architecture to ensure stable operation of circuit and improve reliability of GOA circuit. Moreover, with only two clock signals on each side, the invention is suitable for narrow border display panel.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.

Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.

Abstract: The present invention provides a GOA circuit applied for the In Cell type touch display panel. The third transmission gate (TG3) comprising the second P-type thin film transistor (T2) and the third N-type thin film transistor (T3), the first P-type thin film transistor (T1) and the fourth N-type thin film transistor (T4) are added in the output buffer module (600), and the touch control signal (TCK) and the inverted touch control signal (XTCK) are introduced to control the working status of the output buffer module (600). Thus, in the touch scan stage, the third transmission gate (TG3) is deactivated, and the first, the fourth thin film transistors (T1, T4) are activated, and the gate scan driving signal output end (Gate(N)) is floating, and similarly jumps between high, low voltage levels along with that the touch scan driving signal jumps between high, low voltage levels.

Abstract: The present disclosure relates to a gate driving circuit and the LCD thereof. The input circuit generates second control signals in accordance with up-level normal-phase scanning driving signals, up-level inverting-phase scanning driving signals, and first control signals outputted by the latch circuit. The reset and control circuit generates third control signals in accordance with reset signals, the first control signals, and the second control signals.

Abstract: A gate driving circuit and a liquid crystal display are disclosed. The gate driving circuit includes: an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output buffering circuit electrically connected with the signal processing circuit. Wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel. Each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the two switch modules. The present invention through disposing two switch modules and crosswise connecting the control terminals of the switching tubes, the stress degrees applied on the two switching transistors are the same so as to greatly increase the stability of the circuit operation.

Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.