Patents by Inventor Manish Garg
Manish Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210350134Abstract: A process mining system performs process mining using visual logs generated from video streams of worker devices. Specifically, for a given worker device, the process mining system obtains a series of images capturing a screen of a worker device while the worker device processes one or more tasks related to an operation process. The process mining system determines activity labels for a plurality of images. An activity label for an image may indicate an activity performed on the worker device when the image was captured. The activity label is determined by extracting information from pixels of the image and inferring the activity of the worker device from the extracted information. The process mining system generates event logs from the visual logs of worker devices and uses the event logs for process mining.Type: ApplicationFiled: August 12, 2020Publication date: November 11, 2021Inventors: Manish Garg, Mubarak Abdulla, Sanjyot Gindi, Aanjan Hari, Evgueni Hadjev, Ajay Gabale, Avinash Misra, Anoop Mishra
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Patent number: 11126671Abstract: Computer systems, devices, and associated methods of serializing a web page that is of a first format and includes a plug-in including properties of a second format are disclosed herein. In one embodiment, a method includes identifying, in a manifest for the plug-in, properties for inclusion in the first format in a serialized web page. The manifest may also include metadata associated with the properties in the list of properties. The method includes formatting the properties, including associated property values and metadata, in the first format and adding the formatted properties to the serialized web page. The plug-in properties not included in the manifest can be added to the serialized web page in the second format.Type: GrantFiled: June 29, 2017Date of Patent: September 21, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Patrick Miller, John Nguyen, Manish Garg, Chakkaradeep Chinnakonda Chandran, Daniel Kogan
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Publication number: 20210257689Abstract: An energy storage device includes one or more energy storage cells and at least one holder structure adapted to store at least one energy storage cell of said one or more energy storage cells. Said at least one holder structure includes a composition containing, in weight percent, of a predetermined amount of at least one thermosettable material and an effective amount of at least one curing agent and a predetermined amount of a phase change material. A method of manufacturing said at least holder structure provides high conductivity, high heat absorbing and dissipating capability, improved cooling mechanism, high thermal conductivity and characteristics resulting in minimal risk of electric short circuit between the one or more energy storage cells.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Applicant: TVS MOTOR COMPANY LIMITEDInventors: Manish Garg, Gavhane Santosh Bhagawat, Gundavarapu V S Kumar, Mahajan Subhash Sukhdeorao, Chithambaram Subramoniam, Harne Vinay Chandrakant
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Patent number: 11075624Abstract: A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.Type: GrantFiled: June 19, 2020Date of Patent: July 27, 2021Assignee: STMicroelectronics International N.V.Inventors: Saiyid Mohammad Irshad Rizvi, Manish Garg
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Patent number: 11070198Abstract: A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.Type: GrantFiled: August 27, 2020Date of Patent: July 20, 2021Assignee: STMicroelectronics International N.V.Inventors: Manish Garg, Ankit Agrawal
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Publication number: 20210067144Abstract: A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.Type: ApplicationFiled: August 27, 2020Publication date: March 4, 2021Applicant: STMicroelectronics International N.V.Inventors: Manish GARG, Ankit AGRAWAL
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Publication number: 20200412357Abstract: A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.Type: ApplicationFiled: June 19, 2020Publication date: December 31, 2020Inventors: Saiyid Mohammad Irshad RIZVI, Manish GARG
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Patent number: 10839037Abstract: A method and system for providing a seamless transition between applications is disclosed. The system includes a framework which includes an application manager for managing operations of the system, a component retriever in communications with the application manager for retrieving components associated with the applications, a data retriever in communications with the application manager for retrieving data associated with the applications, a memory for storing the retrieved components or data, and a service group including one or more services associated with applications.Type: GrantFiled: September 21, 2018Date of Patent: November 17, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Aninda Ray, Ryan Antoine Nakhoul, Benjamin James Kaiser, Manish Garg, Ping Jiang, Dennis Joel David Myren, Dmitriy Meyerzon, Marc Pasarin Soler
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Publication number: 20200136595Abstract: A Schmitt trigger circuit includes separate circuits for monitoring change in input signal voltage level in comparison to a low threshold to generate a change in logic state of a first control signal in response to a decrease in a voltage level of the input signal and in comparison to a high threshold to generate a change in logic state of a second control signal in response to an increase in the voltage level of the input signal. A first transistor has a source-drain path connected between a supply node and an output node, with a control terminal of the first transistor configured to receive the second control signal. A second transistor has a source-drain path connected between the output node and a ground node, with a control terminal of the second transistor configured to receive said first control signal.Type: ApplicationFiled: October 24, 2019Publication date: April 30, 2020Applicant: STMicroelectronics International N.V.Inventor: Manish GARG
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Publication number: 20200097611Abstract: A method and system for providing a seamless transition between applications is disclosed. The system includes a framework which includes an application manager for managing operations of the system, a component retriever in communications with the application manager for retrieving components associated with the applications, a data retriever in communications with the application manager for retrieving data associated with the applications, a memory for storing the retrieved components or data, and a service group including one or more services associated with applications.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Aninda RAY, Ryan Antoine NAKHOUL, Benjamin James KAISER, Manish GARG, Ping JIANG, Dennis Joel David MYREN, Dmitriy MEYERZON, Marc PASARIN SOLER
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Patent number: 10559352Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.Type: GrantFiled: September 18, 2018Date of Patent: February 11, 2020Assignee: QUALCOMM IncorporatedInventors: Harish Shankar, Manish Garg, Rahul Krishnakumar Nadkarni, Rajesh Kumar, Michael Phan
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Patent number: 10541044Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.Type: GrantFiled: July 6, 2017Date of Patent: January 21, 2020Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, Viren Ramesh Patel, Michael Phan, Manish Garg, Kevin Magill, Paul Steinmetz, Clint Mumford, Kshitiz Saxena
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Publication number: 20200004550Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Harsh THAKKER, Thomas Philip SPEIER, Rodney Wayne SMITH, Kevin JAGET, James Norris DIEFFENDERFER, Michael MORROW, Pritha GHOSHAL, Yusuf Cagatay TEKMEN, Brian STEMPEL, Sang Hoon LEE, Manish GARG
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Patent number: 10491673Abstract: Systems and methods for synchronizing conversation data between a client and a server in a networked computing environment. A data structure associated with an e-mail conversation is encoded and shuttled between the client and the server. When received at the server, the data structure is analyzed to determine changes within the e-mail conversation. The data structure is subsequently modified to reflect or include only those changes to minimize the amount of information transferred between the server and client.Type: GrantFiled: March 21, 2016Date of Patent: November 26, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Gautam Bhakar, Manish Garg
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Publication number: 20190214076Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.Type: ApplicationFiled: September 18, 2018Publication date: July 11, 2019Inventors: Harish SHANKAR, Manish GARG, Rahul Krishnakumar NADKARNI, Rajesh KUMAR, Michael PHAN
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Publication number: 20190124479Abstract: Cloud-based clinical logging: A method may include obtaining from a first medical device, by a processor, a first datum at a first time; recording the first datum in a database; and transmitting a first message to a first person regarding the first datum if the first datum does not satisfy a pre-determined threshold, where the first message requests an action based on the first datum not satisfying the pre-determined threshold.Type: ApplicationFiled: October 19, 2018Publication date: April 25, 2019Inventors: Raghav Garg, Manish Garg
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Patent number: 10171080Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.Type: GrantFiled: September 20, 2016Date of Patent: January 1, 2019Assignee: QUALCOMM IncorporatedInventor: Manish Garg
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Patent number: 10128845Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.Type: GrantFiled: September 20, 2016Date of Patent: November 13, 2018Assignee: QUALCOMM IncorporatedInventor: Manish Garg
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Patent number: 10050448Abstract: Power rail control systems that include power multiplexing circuits that include cross-current conduction protection are disclosed. Power multiplexing circuit includes supply selection circuits each coupled between a respective supply power rail and an output power rail coupled to a powered circuit. To maintain power to the powered circuit during switching coupling of the output power rail, but while also avoiding current cross-conduction path between supply power rails, diode drop control circuits are provided in supply selection circuits. In diode drop operation mode, the diode drop control circuit associated with a higher voltage supply power rail is configured to regulate voltage supplied by such supply power rail to the output power rail to power the powered circuit. A current cross-conduction path is not created, because diode drop control circuits associated with lower voltage supply power rails are reverse biased to prevent current from flowing through their associated supply selection circuits.Type: GrantFiled: April 15, 2016Date of Patent: August 14, 2018Assignee: QUALCOMM IncorporatedInventors: Yeshwant Nagaraj Kolla, Neel Shashank Natekar, Manish Garg
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Publication number: 20180121274Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.Type: ApplicationFiled: July 6, 2017Publication date: May 3, 2018Inventors: Thomas Philip Speier, Viren Ramesh Patel, Michael Phan, Manish Garg, Kevin Magill, Paul Steinmetz, Clint Mumford, Kshitiz Saxena