Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Abstract: A dual-path, multimode sequential storage element (SSE) is described herein. In one example, the dual-path, multimode SSE comprises first and second sequential storage elements, a data input, a data output, and a selector mechanism. The first and second sequential storage elements each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element and the second sequential storage element comprises a master-slave storage element.

Abstract: A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level.

Abstract: A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

Abstract: A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.

Abstract: A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction.

Abstract: A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions (90) capable of dynamically controlling power dissipation of multiple hardware resources (50-60) during execution of a program by a processor (14). Moreover, a processor (14) configured to process such power control instructions (90) is capable of maintaining the power modes of the multiple hardware resources (50-60) to that specified in an earlier-processed power control instruction (90), such that subsequently-processed instructions (90) will be processed while the power modes of the multiple hardware resources (50-60) are set to that specified by the earlier-processed power control instruction (90).

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: In one embodiment of the invention, a programmable logic block within a programmable logic device includes: a plurality of lookup tables, each lookup table providing a combinatorial output signal; and a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals, wherein the number of registers is less than the number of lookup tables.

Abstract: A dual-path, multimode sequential storage element (SSE) is described herein. In one example, the dual-path, multimode SSE comprises first and second sequential storage elements, a data input, a data output, and a selector mechanism. The first and second sequential storage elements each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element and the second sequential storage element comprises a master-slave storage element.

Abstract: A knowledge management system includes a data recognition engine that dynamically defines metadata to be extracted from a plurality of data sources. A data collection engine is coupled to the data recognition engine to detect and extract the metadata from the plurality of data sources, and a data analysis engine is coupled to the data recognition and data collection engines to link metadata collected from the data collection engine. A search engine is coupled to the data analysis engine to receive output from the data analysis engine.

Abstract: Code coverage analysis for uncompiled code, such as scripts, is performed by instrumenting the scripts with log statements, executing the scripts, and analyzing the scripts. The log statements are appended to discrete blocks of the scripts during the instrumenting and are executed when the corresponding scripts are executed. The log statements cause logs to be written to a log file when the corresponding blocks are executed. The log file is subsequently compared to the original scripts to determine what portion and percentages of the code have been executed. Code coverage data is presented in a variety of formats to the user.

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions (90) capable of dynamically controlling power dissipation of multiple hardware resources (50-60) during execution of a program by a processor (14). Moreover, a processor (14) configured to process such power control instructions (90) is capable of maintaining the power modes of the multiple hardware resources (50-60) to that specified in an earlier-processed power control instruction (90), such that subsequently-processed instructions (90) will be processed while the power modes of the multiple hardware resources (50-60) are set to that specified by the earlier-processed power control instruction (90).

Abstract: A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.

Abstract: A mechanism for retrieving data over a network using an asynchronous buffer is described herein. According to one embodiment, an exemplary process includes, in response to a request for first data from a client via a first thread, determining whether a local circular buffer contains the requested first data, the local circular buffer having a head region and a tail region for identifying a head and a tail of the local circular buffer respectively, and the local circular buffer containing a portion of a data file maintained by a server over a network, generating a second thread to the server over the network to request the first data, if the local circular buffer does not contain the requested first data, and returning the first thread to the client while waiting for a result of the second thread from the server. Other methods and apparatuses are also described.

Abstract: A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level.