Patents by Inventor Manish Kumar

Manish Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150360533
    Abstract: A torsion profile for a twist beam axle of a vehicle is provided and includes a base body having an open hollow cross section. The body comprises first and second end portions adjacent a central portion and a cross section having first and second limbs connected by a central web portion, the cross section having a U-shape or a V-shape. At least one of the limbs varies in length along the longitudinal axis of at least one of the first and second end portions. At least one of the limbs has a flange arranged on a free end thereof, the variation in length of the at least one limb providing the first and second end portions with a continuously varying cross section along the length of the base body.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 17, 2015
    Applicant: FORD GLOBAL TECHNOLGIES, LLC
    Inventors: Manish Kumar SETH, Jens GLORER, Ralf Andreas SCHELLHAAS, Andreas HINZ
  • Publication number: 20150363739
    Abstract: A project team creator is provided that recommends project teams. The project team creator provides a project demand profile and generates a plurality of suggested project teams, the generating including building a graph of each of the plurality of suggested project teams. The project team creator determines a compatibility metric for each of the plurality of suggested project teams and determines a ranking of each of the plurality of suggested project teams based on the corresponding compatibility metric. The project team creator then outputs the ranking of each of the plurality of suggested project teams and the graph of each of the plurality of suggested project teams.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: Vaibhav APARIMIT, Manish KUMAR, Raghavan SRINIVASAN
  • Patent number: 9215133
    Abstract: A policy and charging rules function (PCRF), generates a Diameter audit message concerning an application level Diameter session for which local resources are maintained by the PCRF. The PCRF includes, in the audit message, a fake parameter value. The PCRF sends the audit message with the fake parameter value to the OCS or the AF over an Sy or Rx interface. The PCRF receives a response to the audit message from the OCS or AF. The PCRF determines, based on the response, whether the application level session comprises and orphan session. The PCRF, in response to determining that the application level Diameter session comprises an orphan session frees the local resources maintained by the PCRF for the orphan session.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: December 15, 2015
    Assignee: Tekelec, Inc.
    Inventors: Uri Baniel, Tarek Abou-Assali, Manish Kumar Gupta, Sayan Chowdhury
  • Publication number: 20150347944
    Abstract: A system is provided that visualizes an allocation of resources. The system displays a chart, where the chart includes a list of tasks and a timeline including time units. The system further displays task indicators within the timeline of the chart, where a task indicator includes task indicator segments, and where an area of a task indicator segment is proportional to a work scope of a resource allocated to a corresponding task. The system further receives a user interaction that includes a movement of the task indicator segment from a first task indicator that corresponds to a first task to a second task indicator that corresponds to a second task. The system further allocates the resource from the first task to the second task. The system further modifies the display of at least one task indicator within the timeline of the chart based on the allocation of the resource.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: Oracle International Corporation
    Inventors: Vaibhav APARIMIT, Manish KUMAR, Raghavan SRINIVASAN, Niladri De, Surya Vedula
  • Patent number: 9201994
    Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 1, 2015
    Assignee: Calypto Design Systems, Inc.
    Inventors: Nikhil Tripathi, Vishnu Kanwar, Manish Kumar, Srihari Yechangunja
  • Publication number: 20150310374
    Abstract: A method and system are disclosed for automatically monitoring electronic communications and producing reports relating to staff activity levels. A predetermined set of customer contacts and electronic addresses associated with said contacts is used to relate the metadata of communications to the identified customer contacts. A report compiling a set of data relating the communications to the identified contacts or organisations, identifying the level of communications activity associated with each of said contacts or organisations, can then be produced.
    Type: Application
    Filed: December 4, 2013
    Publication date: October 29, 2015
    Inventors: Steve David ALLAM, Manish Kumar GOEL
  • Patent number: 9146748
    Abstract: The disclosed computer-implemented method for injecting drivers into computing systems during restore operations may include (1) identifying a restore operation directed to restoring a system volume on a computing system, (2) locating, at least in part by examining a hardware configuration of the computing system being restored, at least one driver utilized by the hardware configuration, (3) representing the system volume as an image to a deployment image servicing and management application, and (4) causing the deployment image servicing and management application to inject the driver into the computing system as part of the restore operation. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: September 29, 2015
    Assignee: Symantec Corporation
    Inventor: Manish Kumar
  • Patent number: 9140576
    Abstract: Embodiments of the invention can provide systems and methods for controlling the load of demand response metering devices. According to one embodiment of the invention, a system can be provided. The system can be operable to receive a load limit, store the load limit, determine a load demand of a location, provide an alarm when the load demand is greater than the load limit, and restrict electricity to the location when the load demand remains greater than the load limit for a predetermined amount of time.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 22, 2015
    Assignee: General Electric Company
    Inventors: Balakrishna Pamulaparthy, Manish Kumar Sharma, Aditya Gupta
  • Patent number: 9134997
    Abstract: A method, non-transitory computer readable medium, and apparatus that quantitatively assesses the impact of a project change request to software quality including determining at least one initial project request defect value based on an initial project request effort value and a defect insertion rate, determining at least one project change request defect value based on a project change request effort value and the defect insertion rate, comparing at least one project change request defect value to at least one initial project request defect value, and providing a quality impact value based on the result of the comparison.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 15, 2015
    Assignee: Infosys Limited
    Inventors: Manish Kumar Nema, Jigar Mehta
  • Patent number: 9122823
    Abstract: Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vikas Agarwal, Samantak Gangopadhyay, Manish Kumar
  • Publication number: 20150178427
    Abstract: Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: International Business Machines Corporation
    Inventors: Vikas Agarwal, Samantak Gangopadhyay, Manish Kumar
  • Publication number: 20150126589
    Abstract: The invention discloses a method for expressing an mRNA in lung wherein —the mRNA to be expressed is combined with polyethyleneimine (PEI) to provide a combination comprising the mRNA and PEI; —the combination comprising the mRNA and PEI is administered to lung where it enters lung cells; and —the mRNA is expressed in the lung cells.
    Type: Application
    Filed: June 7, 2013
    Publication date: May 7, 2015
    Inventors: Johannes Geiger, Manish Kumar Aneja, Carsten Rudolph
  • Patent number: 8989056
    Abstract: The subject matter described herein includes systems, methods, and computer readable media for utilizing quota usage policy control in a Diameter-based communication network. An exemplary method includes, at a policy server, sending a request for quota usage information associated with a subscriber to an online charging system (OCS) node. The method further includes receiving the quota usage information from the OCS node, generating at least one policy and charging control (PCC) rule for modifying a quality of service (QoS) policy attribute associated with the subscriber based on the quota usage information, and communicating the at least one PCC rule to a Diameter network element.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 24, 2015
    Assignee: Tekelec, Inc.
    Inventors: Uri Baniel, Manish Kumar Gupta, Joseph Wonseok Lee
  • Publication number: 20150081731
    Abstract: The technique relates to a system and method for selecting process element variants in business processes. The technique involves receiving a process element execution request from at least one user. Then, determining a plurality of enterprise dimensions associated with the process element execution request. Thereafter, searching the process element variant corresponding to the plurality of enterprise dimensions in a declarative way based on a predefined dimensional hierarchy. Finally, selecting the process element variant for execution to accomplish the user request. This technique employs a declarative approach which eliminates the need define the variants for all possible combination of enterprise dimensions namely process, events, locations, organizations and data.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 19, 2015
    Applicant: Infosys Limited
    Inventors: Neeli Basanth Kumar, Manish Kumar
  • Publication number: 20150058477
    Abstract: Command performance may be monitored. In a monitoring transaction, a product may be selected from a plurality of products in one group of a plurality of groups of products. Execution performance of a command by the selected product may be monitored. The monitored execution performance may be provided for determining compliance with a service level agreement for the product based on the monitored executed performance.
    Type: Application
    Filed: June 30, 2014
    Publication date: February 26, 2015
    Inventors: James Gould, Manish Kumar Maheshwari, Sathyabodh Mudhol
  • Patent number: 8958620
    Abstract: A method for cardiac imaging for determining a myocardial region of interest (ROI) is disclosed. The method includes acquiring functional imaging data of a subject, where the functional imaging data includes at least the myocardium. A ROI encompassing at most the myocardium from the acquired functional imaging data, and diagnostic parameters relating to the myocardium are estimated and quantified based on the determined ROI. In one embodiment, the ROI is determined from a projection image representation utilizing histogram based thresholding and ray casting based localization to determine the extents of the ROI. In another embodiment, the ROI is determined from a volumetric image representation utilizing clustering Manhattan distance based cleaning to determine cardiac angles used for reorienting the left ventricle.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: February 17, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Shekhar Dwivedi, Manish Kumar Sharma, Narayan Ayyakad Krishnan, Yogish Mallya
  • Publication number: 20140370554
    Abstract: The present invention is to enhance the stability and enzyme activity of an L-arabitol dehydrogenase derived from Neurospora crassa using techniques from quantum mechanics and molecular mechanics and partial mutation techniques. More specifically, the present invention relates to a method for preparing an L-arabitol dehydrogenase in which a residue which affects enzyme stability is found through a screening based on quantum mechanics and molecular mechanics, and enzyme activity is enhanced by mutation of the found residue, nucleic acid molecules encoding the L-arabitol dehydrogenase, a vector including the nucleic acid molecules, a transformant including the vector, a mutant of the L-arabitol dehydrogenase and an improved L-arabitol dehydrogenase.
    Type: Application
    Filed: April 18, 2013
    Publication date: December 18, 2014
    Inventors: Jung Kul Lee, Hee Jung Moon, Manish Kumar Tiwari, Tae Su Kim
  • Patent number: 8904322
    Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vikas Agarwal, Samantak Gangopadhyay, Shashank Joshi, Manish Kumar
  • Publication number: 20140333287
    Abstract: An integrated circuit includes electronic components, a voltage regulator for generating a control voltage, and a power consumption measurement module. The power consumption measurement module is connected to the voltage regulator and includes an analog-to-digital converter (ADC) for converting the control voltage to multiple digital control voltage samples, an averaging module for averaging the digital control voltage samples, and a current profiling module for receiving the averaged control voltage data and determining an average current from averaged control voltage data. The average current represents power consumption of the integrated circuit.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Inventors: Sunny Gupta, Kumar Abhishek, Manish Kumar, Himanshu Singhal
  • Publication number: 20140298282
    Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a pluraility of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Vikas Agarwal, Samantak Gangopadhyay, Shashank Joshi, Manish Kumar