Patents by Inventor Manish Shah

Manish Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190216472
    Abstract: The present jig for guiding placement of femoral component of the implant in a knee replacement surgery (J) is a pre-assembled Jig (J) that ensures precision fit femoral implant for knee replacement based on difference of cuts in millimeters instead of the usual angle measurement in degrees. It avoids intrusion of the intramedullary canal substantially decreasing the risks of embolism. It enables the surgeon to use precise values of depth of cuts obtained from a system for obtaining optimum fit implant as described in patent application number 3896/MUM2015. This enables the surgeon to control precisely the placement of the implant in terms of flexion or extension, varus or valgus, internal or external rotation. It also enables precise placement of the four-in-one cutting block simultaneously with the distal femur cut; ensuring precise placement of knee femoral component of the knee implant. This reduces efforts and time taken during surgery.
    Type: Application
    Filed: July 19, 2017
    Publication date: July 18, 2019
    Inventor: Manish Shah
  • Patent number: 10346487
    Abstract: A data attribution system uses a unique identifier (UID) that uniquely identifies a particular individual. A search is conducted of different data sources and, different types of profile information associated with the UID is extracted from the data sources. The different types of profile information associated with the same UID is aggregated together and displayed in a same screen presentation on a user interface.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 9, 2019
    Assignee: LIVERAMP, INC.
    Inventors: Auren Hoffman, Manish Shah, Jeremy Lizt, Vivek Sodera
  • Patent number: 10318303
    Abstract: A method and apparatus for performing branch prediction is disclosed. A branch predictor includes a history buffer configured to store a branch history table indicative of a history of a plurality of previously fetched branch instructions. The branch predictor also includes a branch target cache (BTC) configured to store branch target addresses for fetch addresses that have been identified as including branch instructions but have not yet been predicted. A hash circuit is configured to form a hash of a fetch address, history information received from the history buffer, and hit information received from the BTC, wherein the fetch address includes a branch instruction. A branch prediction unit (BPU) configured to generate a branch prediction for the branch instruction included in the fetch address based on the hash formed from the fetch address, history information, and BTC hit information.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 11, 2019
    Assignee: Oracle International Corporation
    Inventors: Manish Shah, Jared Smolens
  • Patent number: 10255197
    Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: April 9, 2019
    Assignee: Oracle International Corporation
    Inventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
  • Patent number: 10198260
    Abstract: A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 5, 2019
    Assignee: Oracle International Corporation
    Inventors: Manish Shah, Christopher Olson
  • Publication number: 20180285114
    Abstract: A method and apparatus for performing branch prediction is disclosed. A branch predictor includes a history buffer configured to store a branch history table indicative of a history of a plurality of previously fetched branch instructions. The branch predictor also includes a branch target cache (BTC) configured to store branch target addresses for fetch addresses that have been identified as including branch instructions but have not yet been predicted. A hash circuit is configured to form a hash of a fetch address, history information received from the history buffer, and hit information received from the BTC, wherein the fetch address includes a branch instruction. A branch prediction unit (BPU) configured to generate a branch prediction for the branch instruction included in the fetch address based on the hash formed from the fetch address, history information, and BTC hit information.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Manish Shah, Jared Smolens
  • Publication number: 20180275724
    Abstract: Reversible connector orientation detection circuitry, reversibly connectible devices having multiple device portions, and methods for determining a connection orientation of multiple device portions of a hardware device are provided herein. A hardware device can include a first device portion and a second device portion. A first resistor can be in a first side of the first device portion. A second resistor can be in a first side of the second device portion, and a third resistor can be in a second side of the second device portion. Connection of the first device portion to the second device portion in different orientations creates, through the resistors, different voltages that can be compared by a digital logic device to indicate orientation. The compared voltages are within either a low voltage range below a digital logic low threshold or a high voltage range above a digital logic high threshold.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 27, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: James Hao-An Chen Lin, Jyhlin Chang, Manish Shah
  • Publication number: 20180225239
    Abstract: A system is disclosed, including a plurality of access units, a plurality of circuit nodes each coupled to a respective access unit, and a plurality of data processing nodes each coupled to a respective access unit. A particular data processing node may be configured to generate a plurality of data transactions. The particular data processing node may also be configured to determine an availability of a coupled access unit. In response to a determination that the coupled access unit is unavailable, the particular data processing node may be configured to halt a transfer of the plurality of data transactions to the coupled access unit and assert a halt indicator signal. In response to a determination that the coupled access unit is available, the particular data processing node may be configured to transfer the particular data transaction to the coupled access unit.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Robert Golla, Manish Shah, Mark Luttrell
  • Patent number: 10001998
    Abstract: Embodiments for a processor that selectively enables and disables branch prediction are disclosed. The processor may include counters to track a number of fetched instructions, a number of branches, and a number of mispredicted branches. A misprediction threshold may be calculated dependent upon the tracked number of branches and a predefined misprediction ratio. Branch prediction may then be disabled when the number of mispredictions exceed the determined threshold value and dependent upon the branch rate.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: June 19, 2018
    Assignee: Oracle International Corporation
    Inventors: Haowei Zhang, Xiaoying Shen, Manish Shah
  • Publication number: 20180121200
    Abstract: An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 3, 2018
    Inventors: Yuan Chou, Manish Shah
  • Publication number: 20180060075
    Abstract: An apparatus is disclosed, the apparatus including a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 1, 2018
    Inventors: Yuan Chou, Manish Shah, Richa Aggarwal
  • Publication number: 20180024941
    Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.
    Type: Application
    Filed: July 20, 2016
    Publication date: January 25, 2018
    Inventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
  • Patent number: 9855229
    Abstract: The present patent application relates to treatment of a respiratory disorder using retinoid-related orphan receptor gamma t (ROR-gamma) modulators. Particularly, the present patent application relates to treatment of a respiratory disorder using a ROR? inhibitor, wherein the ROR? inhibitor is administered by an inhalation route to a subject in need thereof.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 2, 2018
    Assignee: GLENMARK PHARMACEUTICALS S.A.
    Inventors: Neelima Khairatkar-Joshi, Abhay Kulkarni, Daisy Manish Shah, Vikram Mansingh Bhosale, Bhavik Jaysukhlal Lodhiya, Alamelu Mangai Thiraviam, Megha Marathe, Avinash Annaso Hadambar
  • Publication number: 20170308536
    Abstract: Aspects extend to methods, systems, and computer program products for ranking contextual metadata to generate relevant data insights. Aspects of the invention can be used to enhance data analytics by automatically deriving relevance signals used to generate insights closely related to the context in which a user is exploring or analyzing data. User experiences can include embedded data visualizations, search engines, and natural language querying systems to help users understand their data more effectively. By utilizing metrics on the relevance information, insights related and/or relevant to the context in which the user is analyzing data can be created. Thus, relevance information can define a scope for a variety of automatically generated insights of data. Insight generation can be based on computed relevance signals that target areas interesting to users.
    Type: Application
    Filed: June 16, 2016
    Publication date: October 26, 2017
    Inventors: Saliha Azzam, Steven Paul Breyer, Eeshan Manish Shah, Youssef El Fassy Fihry, Ankur Satyendrakumar Sharma, Manal Hussein Alassaf, Xiang He, Vikram Rajasekaran
  • Publication number: 20170199741
    Abstract: A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventors: Manish Shah, Christopher Olson
  • Patent number: 9682977
    Abstract: The present disclosure is directed to compounds of formula (I) and pharmaceutically acceptable salts thereof, wherein X, X1, M, R2, R3, R4, R5, m, n, and p are as defined herein, which are active as modulators of retinoid-related orphan receptor gamma t (ROR?t). These compounds prevent, inhibit, or suppress the action of ROR?t and are therefore useful in the treatment of ROR?t mediated diseases, disorders, syndromes or conditions such as, e.g., pain, inflammation, COPD, asthma, rheumatoid arthritis, colitis, multiple sclerosis, neurodegenerative diseases and cancer.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: June 20, 2017
    Assignee: GLENMARK PHARMACEUTICALS S.A.
    Inventors: Sanjib Das, Sachin Sundarlal Chaudhari, Abraham Thomas, Shailesh Ramesh Pardeshi, Vishal Govindrao Deshmukh, Prashant Dilip Wadekar, Neelima Khairatkar-Joshi, Daisy Manish Shah, Malini Bajpai
  • Publication number: 20170139706
    Abstract: An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 18, 2017
    Inventors: Yuan Chou, Gideon Levinsky, Manish Shah, Robert Golla, Matthew Smittle
  • Publication number: 20160346234
    Abstract: The present patent application relates to treatment of a respiratory disorder using retinoid-related orphan receptor gamma t (ROR-gamma) modulators. Particularly, the present patent application relates to treatment of a respiratory disorder using a ROR? inhibitor, wherein the ROR? inhibitor is administered by an inhalation route to a subject in need thereof.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 1, 2016
    Inventors: Neelima KHAIRATKAR-JOSHI, Abhay KULKARNI, Daisy Manish SHAH, Vikram Mansingh BHOSALE, Bhavik Jaysukhlal LODHIYA, Alamelu Mangai THIRAVIAM, Megha MARATHE, Avinash Annaso HADAMBAR
  • Publication number: 20160326163
    Abstract: The present disclosure is directed to compounds of formula (I) and pharmaceutically acceptable salts thereof, wherein X, X1, M, R2, R3, R4, R5, m, n, and p are as defined herein, which are active as modulators of retinoid-related orphan receptor gamma t (ROR?t). These compounds prevent, inhibit, or suppress the action of ROR?t and are therefore useful in the treatment of ROR?t mediated diseases, disorders, syndromes or conditions such as, e.g., pain, inflammation, COPD, asthma, rheumatoid arthritis, colitis, multiple sclerosis, neurodegenerative diseases and cancer.
    Type: Application
    Filed: December 9, 2014
    Publication date: November 10, 2016
    Inventors: Sanjib DAS, Sachin Sundarlal CHAUDHARI, Abraham THOMAS, Shailesh Ramesh PARDESHI, Vishal Govindrao DESHMUKH, Prashant Dilip WADEKAR, Neelima KHAIRATKAR-JOSHI, Daisy Manish SHAH, Malini BAJPAI
  • Publication number: 20160089520
    Abstract: A method of using a catheter assembly for inserting in a fluid filled space in a body includes providing a main body having a first end portion and a second end portion. The first end portion is positioned within the fluid filled space. The second end portion is adjusted to extend outwardly from the fluid filled space when the first end portion is positioned within the fluid filled space. A catheter tip is connected to the second end portion of the main body. The catheter tip includes a housing having a cavity defined therein and a rotating element positioned within the fluid filled space. The rotating element is rotated within the cavity of the housing to impart movement of the first end portion of the main body within the fluid filled space.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Inventors: Eric Leuthardt, Guy Genin, Matthew Smyth, David Limbrick, Daniel Moran, Lihong Wang, Aaron McLaughlin, Manish Shah, Alexander Yang, Samuel Stone, Devon Haydon, Michael Winek, Richard Marcus