Abstract: A method, apparatus, and system for configuring an address bit in a cache formed on an integrated circuit. The method, apparatus, and system include the ability to configure the address bit as either a tag bit or a set index bit and reconfigure the address bit.

Abstract: A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog® is generated for the evaluate phase of a dynamic circuit. Second, “comment-logic” in Verilog® syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the “clk=0” and the “clk=1” conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art.

Abstract: A method to collect address trace of instructions executed by a processor has been disclosed. An embodiment of the method includes receiving a software program having a set of instructions and performing instrumentation on the software program to determine addresses of the instructions of the software program in the order in which the instructions are executed by a processor.

Abstract: A method for characterizing a timing value of a timing-sensitive digital logic circuit includes (a) setting a set of input signal parameters such that the transition edge of an input signal is placed a selected time interval from an active edge of a clock signal, (b) conducting a circuit simulation, (c) observing an output signal and determining validity thereof, (d) shifting the transition edge by a window having a given time width, (e) simulating the circuit so as to determine the validity of the output signal, (f) iterating the shifting and the simulating by doubling the time width of the window for each iteration unless the doubled time width exceeds half the clock cycle and until the validity of the output signal changes, and (g) defining a solution window between the transition edge yielding the last valid output signal and the transition edge yielding the last invalid output signal.

Abstract: The present invention relates a drug delivery device which comprises a single phase matrix of two oppositely charged polymers (one positive and one negative), which releases a drug by combined mechanisms employing hindered diffusion, swelling and erosion. The present invention also relates to a method for employing these devices.

Abstract: This invention provides methods for the localized delivery of supplemented tissue sealants, wherein the supplemented tissue sealants comprise at least one composition which is selected from one or more antibodies, analgesics, anticoagulants, anti-inflammatory compounds, antimicrobial compositions, antiproliferatives, cytokines, cytotoxins, drugs, growth factors, interferons, hormones, lipids, demineralized bone or bone morphogenetic proteins, cartilage inducing factors, oligonucleotides polymers, polysaccharides, polypeptides, protease inhibitors, vasoconstrictors or vasodilators, vitamins, minerals, stabilizers and the like. Further provided are methods of using the site-specific supplemented tissue sealants, including preparation of a biomaterial.